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STK17T88
32K x 8 AutoStore nvSRAM with
Real Time Clock
Features
■
Description
The Cypress STK17T88 combines a 256 Kb nonvolatile static
RAM (nvSRAM) with a full-featured real-time clock in a reliable,
monolithic integrated circuit.
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
QuantumTrap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the
STORE
operation). On power up,
data is automatically restored to the SRAM (the
RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
nvSRAM Combined With Integrated Real-Time Clock
Functions (RTC, Watchdog Timer, Clock Alarm, Power
Monitor)
Capacitor or Battery Backup for RTC
25, 45 ns Read Access and R/W Cycle Time
Unlimited Read/Write Endurance
Automatic Nonvolatile STORE on Power Loss
Nonvolatile STORE Under Hardware or Software Control
Automatic RECALL to SRAM on Power Up
Unlimited RECALL Cycles
200K STORE Cycles
20-Year Nonvolatile Data Retention
Single 3V +20%, -10% Power Supply
Commercial and Industrial Temperatures
48-Pin 300-mil SSOP Package (RoHS Compliant)
■
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
en
de
d
fo
rN
m
Quantum Trap
512 X 512
STORE
ew
V
CC
POWER
CONTROL
STORE/
RECALL
CONTROL
R
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
ROW DECODER
om
ec
STATIC RAM
ARRAY
512 X 512
RECALL
D
V
CAP
RTC
MUX
ot
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
N
es
i
V
RTCbat
V
RTCcap
HSB
SOFTWARE
DETECT
A
0
A
1
A
2
A
3
A
4
A
10
A
14
– A
0
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-52040 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 25, 2009
[+] Feedback
gn
s
A
13
– A
0
X
1
X
2
INT
STK17T88
Contents
Features................................................................................ 1
Description........................................................................... 1
Logic Block Diagram........................................................... 1
Contents ............................................................................... 2
Pin Configurations .............................................................. 3
Pin Descriptions .................................................................. 3
Absolute Maximum Ratings ............................................... 4
RF (SSOP-48) Package Thermal
Characteristics................................................................ 4
DC Characteristics (V
CC
= 2.7V-3.6V) ............................... 4
AC Test Conditions ............................................................. 5
Capacitance ......................................................................... 5
RTC DC Characteristics ...................................................... 6
SRAM READ Cycles #1 and #2........................................... 7
SRAM WRITE Cycles #1 and #2 ......................................... 8
AutoStore/Power Up RECALL ............................................ 9
Software-Controlled STORE/RECALL Cycle................... 10
Hardware STORE Cycle .................................................... 11
Soft Sequence Commands ............................................... 11
Mode Selection .................................................................. 12
nvSRAM Operation............................................................ 13
SRAM READ ................................................................ 13
SRAM WRITE .............................................................. 13
AutoStore Operation..................................................... 13
Hardware STORE (HSB) Operation............................. 13
Hardware Recall (POWER UP).................................... 13
Software STORE..........................................................
Software RECALL ........................................................
Data Protection.............................................................
Noise Considerations ...................................................
Preventing AutoStore ...................................................
Best Practices ..............................................................
Real Time Clock.................................................................
Reading the Clock ........................................................
Setting the Clock ..........................................................
Backup Power ..............................................................
Stopping and Starting the RTC Oscillator ....................
Calibrating The Clock ...................................................
Alarm ............................................................................
Watchdog Timer ...........................................................
Power Monitor ..............................................................
Interrupt Register..........................................................
Flags Register ..............................................................
RTC Register Map..............................................................
Commercial and Industrial
Ordering Information.........................................................
Ordering Codes .................................................................
Package Diagram...............................................................
Document History Page ....................................................
Sales, Solutions, and Legal Information .........................
Worldwide Sales and Design Support..........................
Products .......................................................................
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Document Number: 001-52040 Rev. *C
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Page 2 of 24
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STK17T88
Pin Configurations
Figure 1. 48-Pin SSOP
V
CAP
NC
A
14
A
12
A
7
A
6
A
5
INT
A
4
NC
NC
NC
V
SS
NC
V
RTCbat
DQ
0
A
3
A
2
A
1
A
0
DQ
1
DQ
2
X
1
X
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
NC
HSB
W
A
13
A
8
A
9
NC
NC
NC
NC
V
SS
NC
V
RTCcap
DQ
6
G
A
10
E
DQ
7
DQ
5
DQ
4
DQ
3
V
CC
A
11
Relative PCB Area Usage
[1]
Pin Descriptions
Pin Name
A
14
-A
0
DQ
7
-DQ
0
E
W
G
X
1
X
2
V
RTCcap
V
RTCbat
V
CC
HSB
I/O Type
Input
I/O
Input
Input
Input
Output
Input
en
de
d
Address:
The 15 address inputs select one of 32,768 bytes in the nvSRAM array or one of 16 bytes
in the clock register map.
Data:
Bi-directional 8-bit data bus for accessing the nvSRAM and RTC.
N
Power Supply
Power Supply
I/O
ot
Power Supply
INT
V
CAP
V
SS
NC
Output
Power Supply
Power Supply
No Connect
Note
1. For detailed package size specifications, see
Package Diagram
on page 23.
Document Number: 001-52040 Rev. *C
R
ec
Output Enable:
The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tristate.
Crystal Connection, Drives Crystal on Startup.
Crystal Connection for 32.768 kHz Crystal.
Capacitor Supplied Backup RTC Supply Voltage
(Left unconnected if V
RTCbat
is used).
Battery Supplied Backup RTC Supply Voltage
(Left unconnected if V
RTCcap
is used).
Power:
3.0V, +20%, -10%
Hardware Store Busy:
When low this output indicates a store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection Optional).
Interrupt Control:
Can be programmed to respond to the clock alarm, the watchdog timer and the
power monitor. Programmable to either active high (push/pull) or active low (open-drain)
AutoStore Capacitor:
Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
Ground.
Unlabeled Pins have no Internal Connections.
om
Write Enable:
The active low W enables data on the DQ pins to be written to the address location
selected on the falling edge of E.
m
Chip Enable:
The active low E input selects the device.
fo
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Page 3 of 24
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STK17T88
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to V
SS
...........–0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB ......................–0.5V to (V
CC
+ 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Junction Temperature ................................... –55°C to 140°C
Storage Temperature .................................... –65°C to 150°C
Power Dissipation............................................................. 1W
DC Output Current (1 output at a time, 1s duration).... 15 mA
Note
Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
RF (SSOP-48) Package Thermal Characteristics
θ
jc
6.2 C/W;
θ
ja
51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm]
I
CC1
Average V
CC
Current
en
de
d
I
CC3
Average V
CC
Current at t
AVAV
= 200 ns
3V, 25°C, Typical
Average V
CAP
Current during
AutoStore Cycle
V
CC
Standby Current
(Standby, Stable CMOS
Levels)
Input Leakage Current
10
fo
I
CC2
Average V
CC
Current during
STORE
3
rN
3
10
I
CC4
I
SB
3
3
om
m
3
3
ec
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
V
CC
V
CAP
NV
C
DATA
R
Note
■
■
±1
±1
±1
±1
R
Off-State Output Leakage
Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
Storage Capacitance
Nonvolatile STORE Opera-
tions
Data Retention
ot
2.0
V
CC
+ 0.5
2.0
V
CC
+ 0.5
V
SS
- 0.5
0.8
V
SS
- 0.5
0.8
2.4
2.4
0.4
0.4
0
70
- 40
85
2.7
3.6
2.7
3.6
17
57
17
57
200
200
20
20
N
The HSB pin has I
OUT
=-10 µA for V
OH
of 2.4V, this parameter is characterized but not tested.
The INT is open-drain and does not source or sink high current when interrupt register bit D3 is low.
Page 4 of 24
Document Number: 001-52040 Rev. *C
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mA
mA
mA
mA
mA
mA
μA
μA
V
V
V
V
°C
V
μF
K
Symbol
Parameter
Commercial
Min
Max
65
50
Industrial
Min
Max
70
55
Units
D
Notes
t
AVAV
= 25 ns
t
AVAV
= 45 ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care, V
CC
= Max
Average current for duration of STORE
cycle (t
STORE
)
W
≥
(V
CC
– 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (t
STORE
)
E
≥ (V
CC
-0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
-0.2V)
Standby current level after nonvolatile
cycle complete
V
CC
= Max
V
IN
= V
SS
to V
CC
V
CC
= Max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 2 mA
I
OUT
= 4 mA
3.0V +20%, -10%
Between V
CAP
pin and V
SS
, 5V rated.
Years At 55°C
DC Characteristics
(V
CC
= 2.7V-3.6V)
es
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