Stratum 3+
Timing Module
(STM-S3+, 3.3V)
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Application
The Connor-Winfield Stratum 3+ Simplified
Control Timing Module acts as a complete
system clock module for Stratum 3+ timing
applications in accordance with GR-1244-
CORE, Issue 2 and GR-253-CORE, Issue 3.
Connor-Winfield’s Stratum 3+ Timing
module helps reduce the cost of your design
by minimizing your development time and
maximizing your control of the system clock
with our simplified design.
Features
•
Dual Input
References
•
Hitless Switch Over
•
8 kHz - 38.88 MHz
Sync_Out Range
• 8 kHz Independent
Output
•
±39 ppb Composite
Hold Over Mode
•
Fast Acquisition
Mode
•
Hold Over Good
Indicator
•
LOR Alarms
•
Reference
Frequency Limit
Alarm
Bulletin
Page
Revision
Date
Issued By
TM040
1 of 10
P01
24 Oct 02
MBATTS
General Description
Connor-Winfield’s STM-S3+ timing module provides
Stratum 3+ synchronization for a complete system clock
solution in a single module in accordance with GR-1244-
CORE Issue 2, and GR-253-CORE Issue 3. The STM-S3+
provides a reliable network element clock reference to line
cards used in TDM, PDH, SONET, and SDH application
environments. Typical applications include digital cross talks,
DSLAMs, ADMs, multiservice platforms, switches and
routers.
The STM-S3+ meets ±39 ppb Hold Over requirements over
0° – 70°C temperature range. The 3.3V power requirement
will draw a maximum of 1.6 A during an initial start-up period
and then drop to a typical current of 1.2 A during normal
operating conditions. It accepts two 8 kHz input references
and can be manufactured to supply a fixed frequency from 8
kHz to 38.88 MHz.
The STM-S3+ offers 4 user selectable modes of operation,
Reference 1, Reference 2, Hold Over and Free Run. Mode
of operation is selected by two control pins (Table 6). The
current mode of operation is also indicated by two status
pins (Table 7). Free Run is the default mode if no control
signals are asserted on the control pins.
Reference 1 mode and Reference 2 mode are the two
primary operating modes. When the module is locked to a
valid reference, any time after initial power up or reset, the
module is considered to be in the normal operating mode.
During normal operation the output frequency is phase
locked to the input reference frequency. The offset between
the input and output is dependant upon the amount of noise
that is present on the reference signal. For input tolerances,
refer to Table 4.
Hold Over mode provides a stable frequency that is
guaranteed to be within ±0.039 ppm over the entire
temperature range for the first 24 hours after entry into Hold
Over. Hold Over is valid 101 seconds after a reference is
selected and continues to do a running average every 8
seconds for the next 1049 seconds. Long-term Hold Over
values are based on a 1049 second moving window
average. Hold Over values are not updated during LOR or
during Fast Acquisition mode. Hold Over values are buffered
for at least 32 seconds to allow enough time to respond to
the RFL alarm.
Free Run is a mode of operation in which the module is not
locked to a reference and its output frequency is solely
dependent on the initial frequency setting of the internal
oscillator. The output frequency in Free Run is guaranteed
to be ±4.6ppm of the nominal frequency.
Fast Acquisition mode is entered whenever Reference 1 or
2 has been selected. After a new reference has been
selected, the module uses internal filtering that limits the
frequency movement to less than 2.9 ppm/sec. By 100
seconds the module switches to a slower 0.1Hz filter. While
in normal mode, if the phase error is greater than 20
µs,
Fast
Acquisition mode will be initiated. Fast Acquisition mode is
further described as fast start mode in GR-1244-CORE,
Issue 3, sec 3.6.
The STM-S3+ may be reset by asserting a logic low signal to
the Reset pin or cycling the power. Using the Reset pin for a
manual reset is the recommend method for resetting the
module. Resetting the module by cycling the power requires
more time due to the restablization of the internal ovenized
oscillator.
The STM-S3+ provides the user with non-interruptive Tri-
State capabilities. By asserting a logic high signal to the Tri-
State pin, the user is able to Tri-State all outputs. While in
Tri-State, the module continues normal operations and
accepts all normal inputs. When the module is released from
Tri-State, all output signals are valid.
The STM-S3+ module provides three output frequencies.
The Sync_Out is the primary synchronized output. It is
phase locked to the input reference during normal operation
and is set to a fixed frequency when operating in Hold Over
or Free Run. Clock_Out provides a frequency output that
comes from an independent, undisciplined, free running
oscillator that is ±4.6 ppm from the nominal frequency. This
output is typically used for reference frequency qualification.
The 8 kHz output is derived from the Sync_Out output.
The STM-S3+ module provides a variety of alarm indicators
to alert the user to multiple conditions that may affect the
overall performance of their system. The LOR (Loss of
Reference) alarm indicates that the active reference has
been lost. RFL (Reference Frequency Limit) indicates that
the Sync_Out frequency is 15 ppm or more from the Free
Run frequency.
The Mode Alarm pin is used to indicate that the module is not
in a normal operating mode. Conditions that will cause the
Mode Alarm to go high are Hold Over, Free Run, or Fast
Acquisition Modes. See Table 8 for a full description of input
control pins and output indicator pins.
The Hold Over Good pin indicates that an initial average has
been acquired to provide a qualified Hold Over frequency.
The module requires approximately 101 seconds from any
reference switch or mode switch to a new reference to
reacquire a valid average before the indicator goes high.
Initially, entry into Hold Over prior to this will result in a Free
Run frequency. After the first Hold Over Good indication,
entry into Hold Over will be the last valid Hold Over
frequency.
The STM-S3+ meets the requirements for wander generation
and wander transfer as required by GR-1244, sections 5.3
and 5.4. Figures 4, 5 and 6 show typical results. It also
complies with phase transient requirements during
Reference Rearrangement, Entry into Hold Over, and 1
µs
transient.
Preliminary Data Sheet #:
TM040
Page 2
of
10
Rev:
P01
Date:
10/24/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Absolute Maximum Rating
Table 1
Symbol
V
CC
V
I
T
s
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
Minimum
-0.3
-0.5
-40
Nominal
Maximum
4.0
5.5
85
Units
Volts
Volts
deg. C
Notes
1.0, 6.0
1.0
1.0
Recommended Operating Conditions
Table 2
Symbol
V
cc
V
IH
V
IL
Parameter
Power Supply Voltage
High level input voltage - CMOS
Low level input voltage - CMOS
Minimum
3.135
2.0
0
Nominal
3.3
Maximum
3.465
5.5
0.8
Units
Volts
Volts
Volts
Notes
6.0
DC Characteristics
Table 3
Symbol
V
OH
V
OL
Parameter
High level output voltage,
I
OH
= -4.0mA, V
CC
= min.
Low level output voltage,
I
OL
= 8.0mA, V
CC
= max.
Minimum
2.4
Nominal
3.3
Maximum
3.6
0.4
Units
Volts
Volts
Notes
2.0
Specifications
Table 4
Parameter
Frequency Range (Sync_Out)
Frequency Range (Clk_Out)
Supply Current
Timing Reference Inputs
Jitter, Wander and Phase Transient Tolerances
Wander Generation
Wander Transfer
Jitter Generation
Jitter Transfer
Phase Transients
Sync_Out (Pin #15) Free Run Accuracy
Clock_Out (Pin #18) Accuracy
Hold Over Stability
Inital Offset
Temperature
Drift
Maximum Hold Over History
Minimum Time for Hold Over
Pull-in/ Hold-in Range
Lock Time
Lock Accuracy
RFL Alarm Limit
Specifications
8 kHz - 38.88 MHz
8 kHz - 51.84 MHz
1.2 A typical, 1.6 A during warm-up (Maximum)
GR-1244-CORE 3.2.1
GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6
GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2
GR-1244-CORE 5.4
GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3
GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1
GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3
±4.6 ppm over temperature range
±4.6 ppm over temperature range
±0.012 ppm (±5°C),
±0.001 ppm
±0.010 ppm
±0.001 ppm
1049 seconds
101 seconds after a reference rearrangement
±17 ppm from Free Run frequency
100 sec.
0.01 ppm (GR-1244-CORE 2.8)
±15 ppm from Free Run frequency
3.0:
4.0:
Hold Over stability is the cumulative fractional frequency offset as described by
GR-1244-CORE, 5.2
Pull-in Range is the maximum frequency deviation from nominal clock rate on the
reference inputs to the timing module that can be overcome to pull into sychronization
with the reference
After 100 seconds at stable temperature (±5° F)
5.0 V module also available
Notes
±0.039 ppm (0°C - 70°C)
±0.001 ppm
±0.035 ppm
±0.003 ppm
3.0
4.0
5.0
NOTES:
1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage
to the device. Operation beyond Recommended Conditons is not implied.
2.0:
Logic is 3.3V CMOS
5.0:
6.0:
Preliminary Data Sheet #:
TM040
© Copyright 2002 The Connor-Winfield Corp.
Page 3
of
10
Rev:
P01
Date:
10/24/02
All Rights Reserved
Specifications subject to change without notice
Pin Description
Table 5
Pin #
1
2
3
4
5
6
7
Connection
Status 0
Status 1
LOR
Future Use
GND
8 kHz Output
Reset
Description
Mode indicator.
Mode indicator.
Loss of Reference indicator. 1 = active reference has been lost.
Reserved for future use. Do not assert this pin.
Ground
Derived from Sync_Out.
Master reset for the module. A low pulse will reset the module. A logic low for a minimum of
1
µs
is recommended to ensure a complete reset. This pin is pulled high
internally.
Tri-State control for all outputs. 1 = Hi-Z condition, 0 = Normal operation. Pin is pulled low
internally.
Indicates that the module has acquired enough data to provide an average Hold Over value.
Alarm indicator output. 1 = Alarm condition, 0 = Normal operation.
Mode control input. Pin is pulled low internally.
Mode control input. Pin is pulled low internally.
Reference frequency limit alarm for the phase locked loop. 1= Unit is ±15 ppm from Free Run freq.
Ground
System clock output
Reserved for future use. Do not assert this pin
Ground
An independent, Stratum 3 clock output with the required ±4.6 ppm accuracy. May be used as
general purpose clock
Reserved for future use. Do not assert this pin
Ground
External reference #2 input
Ground
External reference #1 input
+3.3 Volt DC supply
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Tri-State
Hold Over Good
Mode Alarm
CNTL A
CNTL B
RFL
GND
Sync_Out
Future Use
GND
Clock_Out
Future Use
GND
External Reference 2
GND
External Reference 1
+3.3 V
DC
Control Inputs
Table 6
CNTL B
0
0
1
1
CTNL A
0
1
0
1
Mode Selected
Free Run
Reference 1
Reference 2
Hold Over
Status Outputs
Table 7
Status 1
0
0
1
1
Status 0
0
1
0
1
Mode
Free Run
Reference 1
Reference 2
Hold Over
Preliminary Data Sheet #:
TM040
Page 4
of
10
Rev:
P01
Date:
10/24/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Pin Assignment
Figure 1
+3.3Vdc
External Reference 1
GND
External Reference 2
GND
Future Use
Clock_Out
GND
Future Use
Sync_Out
GND
RFL
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
Status 0
Status 1
LOR
Future Use
GND
8 kHz output
Reset
Tri-State
Hold Over Good
Mode Alarm
CNTL A
CNTL B
Typical Application Setup
Figure 2
3.3 Vdc
Power Supply
+3.3 Vdc
External Reference 1
Network Timing
Reference Input
eg. BITS
GND
External Reference 2
GND
Future Use
Independent
Free Run
Clock_Out
GND
Future Use
System
Clock
Sync_Out
GND
RFL
Status 0
Status 1
LOR
Future Use
GND
8 kHz output
Reset
Tri-State
Hold Over Good
Mode Alarm
CNTL A
CNTL B
System Control
State Machine
Preliminary Data Sheet #:
TM040
© Copyright 2002 The Connor-Winfield Corp.
Page 5
of
10
Rev:
P01
Date:
10/24/02
All Rights Reserved
Specifications subject to change without notice
51单片机
