SEMICONDUCTOR
SYNERGY
256 x 4 ECL RAM
SY100422-3/4/5/7
SY101422-3/4/5/7
SY10422-3/4/5/7
SY100422-3/4/5/7
SY10422-3/4/5/7
SY101422-3/4/5/7
FEATURES
s
Address access time, t
AA
: 3/4/5/7ns max.
s
Block select access time, t
AB
: 2ns max.
s
Write pulse width, t
WW
: 3ns min.
s
Edge rate, tr/tf: 500ps typ.
s
Write recovery times under 5ns
s
Power supply current, I
EE
: –250mA, –200mA
for –5/7ns
s
Superior immunity against alpha particles provides
virtually no soft error sensitivity
s
Built with advanced ASSET™ technology
s
Fully compatible with industry standard 10K/100K
ECL I/O levels
s
Noise margins improved with on-chip voltage and
temperature compensation
s
Open emitter output for easy memory expansion
s
Includes popular Block Select function allowing
individual read/write control over blocks
s
ESD protection of 2000V
s
Available in 24-pin flatpack and 28-pin PLCC and
MLCC packages
DESCRIPTION
The Synergy SY10/100/101422 are 1024-bit Random
Access Memories (RAMs), designed with advanced Emitter
Coupled Logic (ECL) circuitry. The devices are organized
as 256-words-by-4-bits and meet the standard 10K/100K
family signal levels. The SY100422 is also supply voltage-
compatible with 100K ECL, while the SY101422 operates
from 10K ECL supply voltage (–5.2V). All feature on-chip
voltage and temperature compensation for improved noise
margin.
The SY10/100/101422 employ proprietary circuit design
techniques and Synergy’s proprietary ASSET advanced
bipolar technology to achieve extremely fast access, write
pulse width and write recovery times. ASSET uses
proprietary technology concepts to achieve significant
reduction in parasitic capacitance while improving device
packing density. Synergy’s circuit design techniques, coupled
with ASSET, result not only in ultra-fast performance, but
also allow device operation at reduced power levels with
virtually no soft error sensitivity and with outstanding device
reliability in volume production.
BLOCK DIAGRAM
A
0
A
5
A
6
A
7
Y-Decoder/Driver
A
2
A
3
A
4
X-Decoder/
Driver
A
1
Memory Cell Array
WE
SA/WA*
SA/WA
SA/WA
SA/WA
DI
0
BS
0
DO
0
*
SA = Sense Amplifier
WA = Write Amplifier
DI
1
BS
1
DO
1
DI
2
BS
2
DO
2
DI
3
BS
3
DO
3
© 1999 Micrel-Synergy
Rev.: E
Amendment: /0
1
Issue Date: August,1999
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7
SY100422-3/4/5/7
SY101422-3/4/5/7
PIN CONFIGURATIONS
V
EE
A
7
V
CCA
NC
A
2
A
1
A
0
A
6
DO
0
DO
3
V
CC
BS
0
A
3
A
4
DI
2
DI
3
BS
2
DO
2
1
2
3
4
5
6
24 23 22 21 20 19
18
17
Top View
16
Flatpack
15
F24-1
14
13
7 8 9 10 11 12
DO
3
BS
3
V
CC
V
CCA
DO
0
BS
0
4
3
2
1 28 27 26
25
24
DO
2
BS
2
DI
3
NC
DI
2
A
4
A
3
A
5
WE
DI
1
DI
0
BS
1
DO
1
DO
1
BS
1
DI
0
NC
DI
1
WE
A
5
5
6
7
8
9
10
Top View
MLCC (M28-1)
or
PLCC (J28-1)
20
19
11
12 13 14 15 16 17 18
A
7
A
0
A
1
A
6
V
EE
NC
A
2
PIN NAMES
Label
A
0
- A
7
BS
0
- BS
3
WE
DI
0
- DI
3
DO
0
- DO
3
V
CC
V
CCA
V
EE
Function
Address Inputs
Block Select (BS)
Write Enable
Data Input (D
IN
)
Data Output (D
OUT
)
GND (0V)
Output GND (0V)
Supply Voltage
TRUTH TABLE
Input
BS
H
L
L
L
WE
X
L
L
H
D
IN
X
H
L
X
Output
L
L
L
D
OUT
Mode
Disabled
Write “H”
Write “L”
Read
NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
2
BS
3
23
22
21
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7
SY100422-3/4/5/7
SY101422-3/4/5/7
FUNCTIONAL DESCRIPTION
The Synergy SY10/100/101422 are 1024-bit RAMs
organized as four 256-by-1-bit blocks with each block having
its own Block Select (BS) control signal that functions
essentially like a unique chip select for the Block. The four
blocks and Block Selects together make the device a 256 x
4-bit RAM. Memory cell selection is achieved by using the
8 address bits designated as A
0
through A
7
. Each of the 2
8
possible input address combinations corresponds to a unique
word location in memory. The active low Block Select (BS)
control signals are provided for memory expansion and for
independent control of each of the four 256 x 1-bit blocks of
memory. The active low Write Enable (WE) controls the
read and write operation on the selected block or blocks.
Data resident on the D
IN
inputs (DI
0
through DI
3
) is written
into the addressed location only when WE and the Block
Select (BS) associated with each of the D
IN
bits is held
LOW. This allows control of the Write operation to any one,
two, three or all four of the input data bits. In order to
perform a read operation, WE is held high, the Block Select
(BS) associated with each of the four output blocks is held
low, and the non-inverted output data at the addressed
location is transferred to D
OUT
(DO
0
through DO
3
) to be
read out. This allows control of the Read operation to any
one, two, three or all four of the output blocks. Open emitter
outputs are provided for maximum flexibility and memory
expansion by allowing output wire-OR connections. External
termination of 50Ω to –2.0V or an equivalent circuit must be
used to provide the specified output levels.
All outputs are forced to a logic LOW level when the
RAM is being written into (WE = LOW). The output (or
outputs) associated with a block (or blocks) of memory can
be forced to a logic LOW low level by deselecting that block
(or blocks) with its respective Block Select input (BS
0
– BS
3
= HIGH).
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
EE
V
IN
I
OUT
T
C
T
store
Rating
V
EE
Pin Potential
to V
CC
Pin
Input Voltage
DC Output Current
(Output High)
Temperature Under
Bias
Storage Temperature
Value
+0.5 to –7.0
+0.5 to V
EE
–30
–55 to +125
–65 to +150
Unit
V
V
mA
°C
°C
GUARANTEED OPERATING CONDITIONS
Parameter
Supply Voltage
(1)
Case Temperature
Supply Voltage
(1)
Case Temperature
Supply Voltage
(1)
Case Temperature
NOTE:
1. Referenced to V
CC
.
Symbol Min.
10K
100K
101K
V
EE
T
C
V
EE
T
C
V
EE
T
C
–5.46
0
–4.8
0
–5.46
0
Typ.
–5.2
—
–4.5
—
–5.2
—
Max. Unit
–4.94
75
–4.2
85
–4.94
85
V
°C
V
°C
V
°C
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS
are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections
of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions
for extended periods may affect device reliability.
RISE AND FALL TIME
Parameter
Output Rise Time
Output Fall Time
Code
(1)
Symbol Min. Typ. Max. Unit
F
S
F
S
t
r
t
f
—
—
500
1500
500
1500
—
—
ps
ps
CAPACITANCE
Parameter
Input Pin
Capacitance
Output Pin
Capacitance
Symbol
C
IN
C
OUT
Min.
—
—
Typ.
4
5
Max.
—
—
Unit
pF
pF
NOTE:
1. F = Fast Edge Rate
S = Standard Edge Rate
3
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7
SY100422-3/4/5/7
SY101422-3/4/5/7
10K DC ELECTRICAL CHARACTERISTICS
V
CC
= 0V; T
C
= 0°C to +75°C; V
EE
= –5.2V; Airflow > 2.5m/s; Output Load = 50Ω to –2.0V
Symbol
V
OH
Parameter
Output High Voltage
T
C
0°C
+25°C
+75°C
0°C
+25°C
+75°C
0°C
+25°C
+75°C
0°C
+25°C
+75°C
0°C
+25°C
+75°C
0°C
+25°C
+75°C
0°C to+ 75°C
0°C to +75°C
0°C to +75°C
0°C to +75°C
0°C to +75°C
0°C to +75°C
Min.
–1000
–960
–900
–1870
–1850
–1830
–1020
–980
–920
—
—
—
–1145
–1105
–1045
–1870
–1850
–1830
0.0
–2
30
40
–2
0.0
–250
–200
Max.
–840
–810
–720
–1665
–1650
–1625
—
—
—
–1645
–1630
–1605
–840
–810
–720
–1490
–1475
–1450
20
2
170
220
35
60
—
—
Unit
mV
Condition
V
IN
= V
IH
Max. or V
IL
Min.
V
OL
Output Low Voltage
mV
V
IN
= V
IH
Max. or V
IL
Min.
V
OHC
Output High Voltage
mV
V
IN
= V
IH
Min. or V
IL
Max.
V
OLC
Output Low Voltage
mV
V
IN
= V
IH
Min. or V
IL
Max.
V
IH
Input High Voltage
mV
Guaranteed Input Voltage High
for All Inputs
Guaranteed Input Voltage Low
for All Inputs
V
IN
= V
IH
Max.
V
IN
= V
IL
Min.
V
IN
= V
IL
Min.
V
IN
= V
IH
Max.
V
IN
= V
IL
Min.
V
IN
= V
IH
Max.
All Inputs and Outputs Open
V
IL
Input Low Voltage
mV
I
IH
I
IL
I
IL
I
IH
I
IL
I
IH
I
EE
Input High Current
Input Low Current
BS Input Low Current
BS Input High Current
WE Input Low Current
WE Input High Current
Power Supply
Current
µA
µA
µA
µA
µA
µA
mA
-3ns, -4ns
-5ns, -7ns 0°C to +75°C
100K/101K DC ELECTRICAL CHARACTERISTICS
V
CCA
= 0V
V
CC
= 0V
Symbol
V
OH
V
OL
V
OHC
V
OLC
V
IH
V
IL
I
IH
I
IL
I
IL
I
IH
I
IL
I
IH
I
EE
V
EE
= –4.5V (100K)
V
EE
= –5.2V (101K)
Parameter
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
BS Input Low Current
BS Input High Current
WE Input Low Current
WE Input High Current
Power Supply
Current
-3ns, -4ns
-5ns, -7ns
Min.
–1025
–1810
–1035
—
–1165
–1810
0.0
–2
30
40
–2
0.0
–250
–200
T
C
= 0°C to +85°C
Max.
–880
–1620
—
–1610
–880
–1475
20
2
170
220
35
60
—
—
Unit
mV
mV
mV
mV
mV
mV
µA
µA
µA
µA
µA
µA
mA
Airflow > 2.5m/s
Output Load = 50Ω to –2.0V
Condition
V
IN
= V
IH
Max. or V
IL
Min.
V
IN
= V
IH
Max. or V
IL
Min.
V
IN
= V
IH
Min. or V
IL
Max.
V
IN
= V
IH
Min. or V
IL
Max.
Guaranteed Input Voltage High
for All Inputs
Guaranteed Input Voltage Low
for All Inputs
V
IN
= V
IH
Max.
V
IN
= V
IL
Min.
V
IN
= V
IL
Min.
V
IN
= V
IH
Max.
V
IN
= V
IL
Min.
V
IN
= V
IH
Max.
All Inputs and Outputs Open
4
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7
SY100422-3/4/5/7
SY101422-3/4/5/7
AC ELECTRICAL CHARACTERISTICS
AC TEST CONDITIONS
V
CC
= V
CCA
= 0V
V
EE
= –5.2V
±
5%(10K)
V
EE
= –4.5V
±
0.3V(100K)
V
EE
= –5.2V
±
5%(101K)
Output Load = 50Ω to –2.0V
T
C
= 0°C to +75°C (10K)
T
C
= 0°C to +85°C (100K/101K)
Airflow > 2.5m/s
T
C
10K
0°C
+25°C
+75°C
0°C to +85°C
V
IH
–0.933V
–0.90V
–0.863V
–0.90V
V
IL
–1.733V
–1.70V
–1.663V
–1.70V
Loading Condition
GND
100/101K
Input Pulse
V
IH
V
CCA
V
CC
OUT
V
EE
R
L
C
L
80%
20%
V
IL
t
r
t
r
= t
f
= 1.0ns typ.
t
f
0.01µF
V
EE
–2.0V
NOTE:
OUTPUT LOAD: R
L
= 50Ω
C
L
= 5pF* (typ.)
* (Modeled as 50Ω transmission line
terminated to –2V.)
All timing measurements referenced to 50% input levels.
READ CYCLE
SY10422-3
SY100422-3
SY101422-3
SY10422-4
SY100422-4
SY101422-4
SY10422-5
SY100422-5
SY101422-5
SY10422-7
SY100422-7
SY101422-7
Symbol
t
AA
t
AB
t
RB
TAVQV
TBSLQV
TBSHQL
Parameter
Address Access Time
Block Select Access Time
Block Select Recovery Time
Min.
—
—
—
Max.
3
2
2
Min.
—
—
—
Max.
4
2
2
Min.
—
—
—
Max.
5
3
3
Min.
—
—
—
Max.
7
3
3
Unit
ns
ns
ns
READ CYCLE TIMING DIAGRAM
BS
50%
t
AB
t
RB
80%
50%
20%
t
r
t
f
D
OUT
Address
50%
t
AA
50%
D
OUT
5
51单片机
