The SY10/100H601 are 9-bit, dual supply ECL-to-TTL
translators. Devices in the Micrel-Synergy 9-bit translator
series utilize the 28-lead PLCC for optimal power pinning,
signal flow-through and electrical performance.
The devices feature a 48mA TTL output stage and AC
performance is specified into both a 50pF and 200pF
load capacitance. For the 3-state output disable, both
ECL and TTL control inputs are provided, allowing
maximum design flexibility.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
OEECL
OETTL
D
0
Q
0
PIN CONFIGURATION
V
CCT
Q
6
GND
Q
5
GND
Q
7
Q
8
25 24 23 22 21 20 19
Q
4
Q
3
V
CCT
Q
2
GND
Q
1
Q
0
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
D
8
D
7
V
CCE
D
6
D
5
D
4
D
3
D
1
D
2
Q
1
Q
2
TOP VIEW
PLCC
15
14
13
12
D
3
ECL
D
4
Q
3
Q
4
TTL
OETTL
NC
OEECL
D
0
D
1
D
5
D
6
D
7
Q
5
Q
6
Q
7
PIN NAMES
Pin
GND
V
CCE
Function
TTL Ground (0V)
ECL V
CC
(0V)
TTL Supply (+5.0V)
ECL Supply (–5.2/–4.5V)
Data Inputs (ECL)
Data Outputs (TTL)
3-State Control (ECL)
3-State Control (TTL)
Rev.: D
Amendment: /0
D
8
Q
8
V
CCT
V
EE
D
0
–D
8
Q
0
–Q
8
OEECL
OETTL
1
V
EE
D
2
Issue Date: February, 1998
Micrel
SY10H601
SY100H601
TRUTH TABLE
LOGIC DIAGRAM
OEECL
L
L
H
X
OETTL
L
L
X
H
D
L
H
X
X
Q
L
H
Z
Z
DC ELECTRICAL CHARACTERISTICS
V
CCT
= 5.0V
±
10%; V
EE
= –4.75V to –5.5V (10H Version); V
EE
= –4.2V to –5.5V (100H Version)
T
A
= 0
°
C
Symbol
I
EE
I
CCH
I
CCL
I
CCZ
I
OS
I
OZH
I
OZL
Parameter
Power Supply Current, ECL
Power Supply Current, TTL
Min.
—
—
—
—
–100
—
—
Max.
46
110
110
105
–225
50
–50
T
A
= +25
°
C
Min.
—
—
—
—
–100
—
—
Max.
46
110
110
105
–225
50
–50
T
A
= +85
°
C
Min.
—
—
—
—
–100
—
—
Max.
50
110
110
105
–225
50
–50
Unit
mA
mA
Condition
—
—
Output Short Circuit Current
Output Disable Current HIGH
Output Disable Current LOW
mA
µA
µA
V
OUT
= 0V
V
OUT
= 2.7V
V
OUT
= 0.5V
AC ELECTRICAL
LOGIC DIAGRAM CHARACTERISTICS
V
CCT
= 5.0V
±
10%; V
EE
= –4.75V to –5.5V (10H Version); V
EE
= –4.2V to –5.5V (100H Version)
T
A
= 0
°
C
Symbol
t
PLH
t
PHL
t
PLZ
t
PHZ
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PZL
t
PZH
t
r
t
f
Parameter
Propagation Delay to Output
Output Disable Time, OEECL
Output Disable Time, OETTL
Output Enable Time, OEECL
Output Enable Time, OETTL
Output Rise/Fall Time
1.0V – 2.0V
Min.
1.7
3.4
3.7
5.4
4.3
7.0
3.5
5.0
4.2
6.0
—
—
Max.
4.8
9.6
6.5
13
7.5
15
6.0
12
7.0
14
1.2
3.0
T
A
= +25
°
C
Min.
1.7
3.4
3.7
5.4
4.3
7.0
3.5
5.0
4.2
6.0
—
—
Max.
4.8
9.6
6.5
13
7.5
15
6.0
12
7.0
14
1.2
3.0
T
A
= +85
°
C
Min.
1.7
3.4
3.7
5.4
4.3
7.0
3.5
5.0
4.2
6.0
—
—
Max.
4.8
9.6
6.5
13
7.5
15
6.0
12
7.0
14
1.2
3.0
Unit
ns
ns
ns
ns
ns
ns
Condition
C
L
= 50pF
C
L
= 200pF
C
L
= 50pF
C
L
= 200pF
C
L
= 50pF
C
L
= 200pF
C
L
= 50pF
C
L
= 200pF
C
L
= 50pF
C
L
= 200pF
C
L
= 50pF
C
L
= 200pF
PRODUCT ORDERING CODE
Ordering
Code
SY10H601JC
SY10H601JCTR
SY100H601JC
SY100H601JCTR
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
2
Micrel
SY10H601
SY100H601
28 LEAD PLCC (J28-1)
Rev. 03
3
Micrel
SY10H601
SY100H601
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD
FAX
SANTA CLARA
WEB
CA 95054 USA
+ 1 (408) 980-9191
+ 1 (408) 914-7878
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
使用ADS1.2的时候进入AXD调试环境回出现“ the session file could not be loaded” 解决方案： 1：将工程文件放在不包含中文路径的目录下。 2：设置AXD- confing Interface 中general中的save and load default session前面的选项去掉。 一：在AXD- options - configure...[详细]
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