Micrel, Inc.
3.3V, PRECISION, 33MHz to 500MHz
PROGRAMMABLE LVPECL AND
LVDS BUS CLOCK SYNTHESIZER
Precision Edge
®
Precision Edge
®
SY89532/33L
SY89532L
SY89533L
FEATURES
Integrated synthesizer plus fanout buffers, clock
drivers , and translator in a single 64-pin package
3.3V
±
10% power supply
Low jitter: <50ps cycle-to-cycle
Low pin-to-pin skew: <50ps
33MHz to 500MHz output frequency range
Direct interface to crystal: 14MHz to 18MHz
LVPECL output (SY89532L),
LVPECL/LVDS outputs (SY89533L)
TTL/CMOS compatible control logic
3 independently programmable output frequency
banks:
• 9 differential output pairs @BankB (LVPECL/LVDS)
• 2 differential output pairs @BankA (LVPECL)
• 2 differential output pairs @BankC (LVPECL)
ExtVCO input allows synthesizer and crystal
interface to be bypassed
Available in 64-pin EPAD-TQFP
Precision Edge
®
DESCRIPTION
The SY89532 and SY89533L programmable clock
synthesizer/drivers are a 3.3V, high-frequency, precision PLL-
based clock driver family optimized for multi-frequency, multi-
processor server and synchronous computing applications
that require the highest precision. These devices integrate the
following blocks into a single monolithic IC:
•
•
•
•
PLL (Phase-Lock-Loop)-based synthesizer
Fanout buffers
Clock generator (dividers)
Logic translation (LVPECL, LVDS)
This level of integration minimizes the additive jitter and
part-to-part skew associated with the discrete alternative,
resulting in superior system-level timing as well as reduced
board space and power. For applications that must interface
to a reference clock, see the SY89534/5.
APPLICATIONS
Servers
Workstations
Parallel processor-based systems
Other high-performance computing
Communications
PRODUCT SELECTION GUIDE
Input
Device
SY89532L
SY89533L
SY89534L
(1)
SY89535L
(1)
Note:
1.Refer to SY89534/35L data sheet for details.
Crystal Reference
X
X
X
X
BankA
Output
BankB
BankC
LVPECL LVPECL LVPECL
LVPECL
LVDS
LVPECL
LVPECL LVPECL LVPECL
LVPECL
LVDS
LVPECL
Precision Edge is a registered trademark of Micrel, Inc.
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: June 2005
Micrel, Inc.
Precision Edge
®
SY89532/33L
PACKAGE/ORDERING INFORMATION
NC
GND
VCCA
VCC_LOGIC
VCC_LOGIC
OUT_SYNC
FSEL_A0
FSEL_A1
FSEL_A2
VCCOA
QA0
/QA0
QA1
/QA1
VCCOB
QB0
Ordering Information
(1)
Part Number
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
/QB0
QB1
/QB1
QB2
/QB2
QB3
/QB3
QB4
/QB4
QB5
/QB5
QB6
/QB6
QB7
/QB7
QB8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC
NC
NC
VCO_SEL
/EXTVCO
EXTVCO
LOOP_REF
LOOP_FILTER
GND
XTAL2
XTAL1
VBB_REF
M(3)
M(2)
M(1)
M(0)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Package
Type
H64-1
H64-1
H64-1
H64-1
H64-1
H64-1
H64-1
H64-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Package
Marking
SY89532LHC
SY89532LHC
SY89532LHC
SY89532LHC
SY89532LHH with
Pb-Free bar-line indicator
SY89532LHH with
Pb-Free bar-line indicator
SY89533LHH with
Pb-Free bar-line indicator
SY89533LHH with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Pb-Free
NiPdAu
Pb-Free
NiPdAu
Pb-Free
NiPdAu
SY89532LHC
SY89532LHCTR
SY89533LHC
SY89533LHCTR
SY89532LHH
SY89532LHHTR
SY89533LHH
SY89533LHHTR
64-Pin EPAD-TQFP (H64-1)
/QC1
QC1
/QC0
QC0
VCCOC
FSEL_C2
FSEL_C1
FSEL_C0
GND
FSEL_B2
FSEL_B1
FSEL_B0
GND
VCCOB
VCCOB
/QB8
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
FUNCTIONAL BLOCK DIAGRAM
FSEL_A0 (LSB)
OUT_Sync
V
CC
_Logic
V
CC
_Logic
FSEL_A1
FSEL_A2
V
CCO
A
V
CCO
B
/QA1
/QA0
GND
V
CCA
QA0
QA1
NC
1
NC
2
NC
3
64
NC
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49 QB0
48 /QB0
3
VCO_SEL
/ExtVCO
ExtVCO
Loop Ref
Loop Filter
GND
XTAL2
XTAL1
4
5
6
7
8
Mux 1
9
10
Oscillator
11
Phase
Detector
Charge
Pump
VCO
(600MHz to
1000MHz)
47 QB1
46 /QB1
Buf
45 QB2
0 = Internal VCO enabled
1 = Internal VCO disabled (default)
VCO Select
2x
3-Bit
Divider A
2, 4, 6, 8,
10, 12,18
5
A
EN
44 /QB2
43 QB3
42 /QB3
41 QB4
40 /QB4
3-Bit
Divider B
2, 4, 6, 8,
10, 12,18
9x
B
EN
3
39 QB5
38 /QB5
37 QB6
36 /QB6
3-Bit
Divider C
2, 4, 6, 8,
10, 12,18
C
EN
35 QB7
34 /QB7
33 QB8
2x
3
32 /QB8
31 V
CCO
B
17
/QC1
18
QC1
19
/QC0
20
QC0
21
22
FSEL_C2
23
FSEL_C1
24
FSEL_C0 (LSB)
25
GND
26
FSEL_B2
27
FSEL_B1
28
FSEL_B0 (LSB)
29
GND
30 V
CCO
B
Clock
Buf
VBB_Ref 12
V
CC
–1.3V
Reference
M-Divide
34, 36, 38, 40, 42
44, 48, 50, 52, 54
56, 60, 70, 72
600MHz to
1000MHz
(MSB) M3 13
M2 14
M1 15
(LSB) M0 16
V
CCO
C
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY89532/33L
PIN DESCRIPTION
Power
Pin Number
60, 61
62
55
30, 31, 50
21
9, 25, 63, 29
(exposed pad)
Pin Name
V
CC_Logic
V
CCA
V
CCO
A
V
CCO
B
V
CCO
C
GND
Ground: Exposed pad must be soldered to a ground plane.
Functional Description
Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
Power for Output Drivers: Connect all V
CCO
pins to 3.3V supply. V
CCO
pins are not
connected internally on the die.
Configuration
Pin Number
4
Pin Name
VCO_SEL
Functional Description
LVTTL/CMOS-Compatible Input: Selects between internal or external VCO. For
external VCO, leave floating. Default condition is logic HIGH. Internal 25k
Ω
pull-up.
When tied LOW, internal VCO is selected.
Analog Input/Output: Provides the reference voltage for PLL loop filter.
Analog Input/Output: Provides the loop filter for PLL. See “External Loop Filter
Considerations” for loop filter values.
LVTTL/CMOS-Compatible Input: Used to change the PLL (Phase-Lock Loop)
feedback divider. Internal 25k
Ω
pull-up. (M0 = LSB). Default is logic HIGH.
See “Feedback Divide Select” table.
LVTTL/CMOS-Compatible Input: Bank C post divide select. Internal 25k
Ω
pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table.
LVTTL/CMOS-Compatible Input: Bank B post divide select. Internal 25k
Ω
pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table.
LVTTL/CMOS-Compatible Input: Bank A post divide select. Internal 25k
Ω
pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select.” FSEL_A0 = LSB.
Banks A,B,C output synchronous control: (LVTTL/CMOS compatible). Internal
25k
Ω
pull-up. After any bank has been programmed, toggle with a HIGH-LOW-
HIGH pulse to resynchronize all output banks.
7
8
13,14,15,16
LOOP REF
LOOP FILTER
M (3:0)
22, 23, 24
26, 27, 28
56, 57, 58
59
FSEL_C (2:0)
FSEL_B (2:0)
FSEL_A (2:0)
OUT_SYNC
Input/Output
Pin Number
1, 2, 3
10, 11
12
5, 6
Pin Name
NC
XTAL2, XTAL1
VBB_REF
/EXT_VCO, EXT_VCO
Functional Description
No Connect: Leave floating.
Crystal Input. Directly connect a series resonant crystal across inputs.
Reference Output Voltage. Used for single-ended input. Maximum sink/source
current = 0.5mA.
Differential “Any In” Compatible Input Pair. Allows for external VCO connection. The “Any
In” input structure accepts many popular logic types. See “Input Interface for ExtVCO
Pins” section for intercace diagrams. Can leave unconnected if using internal VCO.
Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A
(0:2). Terminate outputs with 50Ω to V
CC
–2V. See “Output Termination
Recommendations” section for termination detail.
Bank B Output Drivers: SY89532: 100k LVPECL output drivers.
SY89533: Differential LVDS outputs. See “Output Termination Recommendations”
section for termination detail. Output frequency is controlled by FSEL_B (0:2).
Bank C 100k LVPECL Output Drivers: Output frequency is controlled by
FSEL_C (0:2). Terminate outputs with 50Ω to V
CC
–2V. See “Output Termination
Recommendations” section.
No Connect: Leave floating.
3
51, 52, 53, 54
QA1 to QA0
32–49
QB8 to QB0
17, 18, 19, 20
QC1 to QC0
64
NC
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
Precision Edge
®
SY89532/33L
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
All V
CC
V
IN
V
XTAL 1,2
I
OUT
T
store
θ
JA
Rating
V
CC
Pin Potential to Ground Pin
Input Voltage (except XTAL 1,2 pins)
XTAL 1, 2 Input Voltage
DC Output Current
Storage Temperature
Package Thermal Resistance (Junction-to-Ambient)
With Die attach soldered to GND:
–Still-Air (TQFP)
–200lfpm (TQFP)
–500lfpm (TQFP)
With Die attach NOT soldered to GND:
(2)
–Still-Air (TQFP)
–200lfpm (TQFP)
–500lfpm (TQFP)
–LVPECL outputs
–LVDS outputs
Value
–0.5 to +4.0
–0.5 to V
CCI
(V
CC
–1.9V) to V
CC
–50
±10
–65 to +150
23
18
15
44
36
30
4.3
Unit
V
V
V
mA
mA
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θ
JC
Package Thermal Resistance
(Junction-to-Case)
Notes:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.
2. It is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation.
DC ELECTRICAL CHARACTERISTICS
Power Supply
T
A
= 0
°
C
Symbol
V
CCA(1)
V
CC_LOGIC
V
CCO
A/C
V
CCO
B
I
CC
Parameter
PLL and Logic Supply Voltage
Bank A and C V
CC
Output
Bank B V
CC
Output
LVPECL/LVDS
Total Supply Current
(2)
SY89533L LVDS
Min.
3.0
3.0
3.0
—
—
Typ.
3.3
3.3
3.3
—
275
Max.
3.6
3.6
3.6
260
330
Min.
3.0
3.0
3.0
—
—
T
A
= +25
°
C
Typ.
3.3
3.3
3.3
225
285
Max.
3.6
3.6
3.6
260
330
Min.
3.0
3.0
3.0
—
—
T
A
= +85
°
C
Typ.
3.3
3.3
3.3
—
300
Max.
3.6
3.6
3.6
260
330
Unit
V
V
V
mA
mA
Notes:
1. V
CCA
, V
CC_LOGIC
, V
CCO
A/C. V
CCO
B are
not
internally connected together inside the device. They must be connected together on the PCB.
2. No load. Outputs floating, Banks A, B, and C enabled.
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY89532/33L
DC ELECTRICAL CHARACTERISTICS
LVCMOS/LVTTL Input Control Logic
T
A
= 0
°
C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Min.
2.0
—
—
—
Typ.
—
—
—
—
Max.
—
0.8
—
—
Min.
2.0
—
—
–300
T
A
= +25
°
C
Typ.
—
—
—
—
Max.
—
0.8
150
—
Min.
2.0
—
—
—
T
A
= +85
°
C
Typ.
—
—
—
—
Max.
—
0.8
—
—
Unit
V
V
µA
µA
ExtVCO (pins 5, 6) INPUT
(All V
CC
pins = +3.3V
±10%)
T
A
= 0
°
C
Symbol
V
ID
V
IH
V
IL
Parameter
Differential Input Voltage
Input HIGH Voltage
Input LOW Voltage
Min.
100
(1)
200
(2)
—
T
A
= +25
°
C
Max.
—
—
V
CC
+0.3
T
A
= +85
°
C
Min.
100
(1)
200
(2)
—
Typ.
—
—
—
Min.
100
(1)
200
(2)
—
Typ.
—
—
—
Max.
—
—
V
CC
+0.3
Typ.
—
—
—
Max.
—
—
V
CC
+0.3
Unit
mV
mV
V
V
–0.3
—
—
–0.3
—
—
–0.3
—
—
Notes:
1. V
IN
< 2.4V
2. V
IN
< V
CC
+0.3V
100K LVPECL Outputs
T
A
= 0
°
C
Symbol
V
OH
V
OL
V
BB
Parameter
Output HIGH Voltage
(1)
Output LOW Voltage
(1)
Output Reference Voltage
Min.
V
CC
–1.075
V
CC
–1.860
T
A
= +25
°
C
Max.
Min.
Typ.
—
—
Max.
Min.
V
CC
–0.830 V
CC
–1.075
V
CC
–1.570 V
CC
–1.860
T
A
= +85
°
C
Typ.
—
—
Max.
V
CC
–0.830
V
CC
–1.570
Typ.
—
—
Unit
V
V
V
V
CC
–0.830 V
CC
–1.075
V
CC
–1.570 V
CC
–1.860
V
CC
–1.26 V
CC
–1.32 V
CC
–1.38 V
CC
–1.26 V
CC
–1.32 V
CC
–1.38 V
CC
–1.26 V
CC
–1.32 V
CC
–1.38
Note:
1. 50Ω to V
CC
–2V. Banks A, B, and C enabled.
LVDS Outputs (SY89533L) Bank B QB0:8
(2)
T
A
= 0
°
C
Symbol
V
OD
V
OH
V
OL
V
OCM
∆V
OCM
Parameter
Output Voltage Swing
(2, 3)
Output HIGH Voltage
Output LOW Voltage
Output Common Mode Voltage
(2)
Change in Common Mode
Voltage
(2)
Min.
250
—
0.925
1.125
–50
Typ.
—
—
—
—
—
Max.
450
1.475
—
1.375
50
Min.
250
—
0.925
1.125
–50
T
A
= +25
°
C
Typ.
—
—
—
—
—
Max.
450
1.475
—
1.375
50
Min.
250
—
0.925
1.125
–50
T
A
= +85
°
C
Typ.
—
—
—
—
—
Max.
450
1.475
—
1.375
50
Unit
mV
V
V
V
mV
Notes:
2. 100Ω termination across differential pair.
3.
V
OD
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
5
