256K x 32 SRAM MODULE
SYS32256ZK/LK - 020/25/30/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.7 : January 1999
Description
The SYS32256 is a plastic 8M Static RAM Module
offered in 64 pin ZIP and 64 lead SIMM package,
organised as 256K x 32. The module utilises eight
very fast SRAMs housed in SOJ packages, and
uses double sided surface mount techniques, to
achieve a very high density module.
Four chip selects are used to independently enable
the four bytes. Reading or Writing is executed on
individual or any combination of multiple bytes. Two
pins PD0 & PD1 are used to identify module
memory density where alternative versions of the
JEDEC standard modules can be interchanged.
•
•
•
•
Features
Access Times of 020/25/30/35 ns.
64 Pin ZIP & SIMM JEDEC standard pinouts.
5 Volt Supply ± 10%.
Power Dissipation 35ns:
Operating (32bit mode)
6.60 W (maximum).
Standby (CMOS) -L
4.40 mW (maximum).
Completely Static Operation.
Equal Access and Cycle Times.
All Inputs and Outputs Directly TTL Compatible.
On-board Supply Decoupling Capacitors.
•
•
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•
Block Diagram
A0-A17
OE
WE
256k
x4
CS1
256k
x4
CS2
256k
x4
CS3
256k
x4
CS4
D24-D27
256k
x4
D28-D31
D16-D19
256k
x4
D20-D23
D8-D11
256k
x4
D12-D15
D0-D3
256k
x4
D4-D7
Pin Definition
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
GND
PD1
D8
D9
D10
D11
A0
A1
A2
D12
D13
D14
D15
GND
A15
CS2
CS4
A17
OE
D24
D25
D26
D27
A3
A4
A5
VCC
A6
D28
D29
D30
D31
PD0
D0
D1
D2
D3
VCC
A7
A8
A9
D4
D5
D6
D7
WE
A14
CS1
CS3
A16
GND
D16
D17
D18
D19
A10
A11
A12
A13
D20
D21
D22
D23
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Pin Functions
Address Inputs
Data Input/Output
Chip Select Input
Read/Write Input
Output Enable Input
Power (+5V)
Ground
A0 - A17
D0 - D31
CS1- CS4
WE
OE
V
CC
GND
ISSUE 1.7 January 1999
SYS32256ZK/LK - 020/25/30/35
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Notes :
Symbol
V
T
P
T
T
STG
min
-0.5V
-
-55
typ
-
4.0
-
max
+7.0
-
+125
unit
V
mW
o
C
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at those or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
min
4.5
2.2
-0.3
0
-40
typ
5.0
-
-
-
-
max
5.5
6.0
0.8
70
85
unit
V
V
V
o
o
C
C
(I)
DC Electrical Characteristics
(V
CC
=5V±10%)
Parameter
I/P Leakage Current
Output Leakage Current
Average Supply Current (20/25/30)
Average Supply Current (35/45/55)
Standby Supply Current TTL levels
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB1
T
A
0 to 70
O
C
Test Condition
V
IN
= GND to V
CC,
V
cc
=max.
CS = V
IH,
V
I/O
= GND to V
CC
min
-
-
typ max Unit
-
-
-
-
-
3.20
-
2.4
-
-
±16 µA
±16 µA
1440 mA
1200 mA
320 mA
16 mA
0.4
-
V
V
t
CYC
= 20ns, CS = V
IL
, V
IN
= V
IL
/V
CC
-2.1V -
t
CYC
= 35ns, CS= V
IL
, V
IN
=V
IL
/V
CC
-2.1V
CS = V
CC
-2.1V, V
IL
> V
IN
> V
CC
-2.1V
CS = V
CC
-0.2V, 0.2 > V
IN
> V
CC
-0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
-
-
-
CMOS levels I
SB2
Output Low Voltage
Output High Voltage
V
OL
V
OH
Typical values are at V
CC
=5.0V,T
A
=25
°
C and specified loading.
All values specified for 32 bit operation. I
SB2
= 0.8mA max. for low power option.
2
SYS32256ZK/LK - 020/25/30/35
ISSUE 1.7 January 1999
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Note: Capacitance calculated, not measured.
Parameter
Input Capacitance (CS)
Input Capacitance (other)
I/O Capacitance
Symbol
C
IN1
C
IN2
C
I/O
Test Condition
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
typ
-
-
-
max
12
48
8
Unit
pF
pF
pF
Operation Truth Table
CSn
H
L
L
L
OE
X
L
X
L
WE
X
H
L
L
DATA PINS
High Impedance
Data Out
Data In
Data In
SUPPLY CURRENT
I
SB1
, I
SB2
I
CC1
, I
CC2
I
CC1
, I
CC2
I
CC1
, I
CC2
MODE
Standby
Read
Write (1)
Write (2)
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
Low V
cc
Data Retention Characteristics - L Version Only (T
OP
= 0°C to 70°C)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Symbol Test Condition
V
DR
I
CCDR
CS - V
CC
-0.2V
min
2.0
-
-L Part
typ
(1)
-
16
max
-
400
Unit
V
µA
0.2V
≥
V
in
≥
V
cc
-0.2
V
CC
= 3.0V, CS = V
CC
-0.2V
0.2V
≥
V
in
≥
V
cc
-0.2
t
CDR
t
R
See Retention Waveform
See Retention Waveform
0
5
-
-
-
-
ns
ms
Notes (1) Typical figures are measured at 25°C.
AC Test Conditions
* Input pulse levels: Vss to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
= 5V± 10%
Output Load
I/O Pin
166Ω
1.76V
30pF
3
ISSUE 1.7 January 1999
SYS32256ZK/LK - 020/25/30/35
AC OPERATING CONDITIONS
Read Cycle
(1,2)
-020
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
20
-
-
-
3
3
0
0
0
max
-
20
20
10
-
-
-
12
10
-25
min
25
-
-
-
3
3
0
0
0
max
-
25
25
13
-
-
-
15
10
-30
min
30
-
-
-
3
3
0
0
0
max
-
30
30
15
-
-
-
15
12
-35
min
35
-
-
-
3
3
0
0
0
max
-
35
35
20
-
-
-
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-020
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
(3)
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
20
17
0
15
15
0
0
12
0
0
max
-
-
-
-
-
-
8
-
-
-
min
25
20
0
20
20
0
0
15
0
0
-25
max
-
-
-
-
-
-
10
-
-
-
-30
min
30
25
0
25
22
0
0
18
0
0
max
-
-
-
-
-
-
12
-
-
-
-35
min
35
30
0
30
25
0
0
20
0
0
max
-
-
-
-
-
-
15
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
SYS32256ZK/LK - 020/25/30/35
ISSUE 1.7 January 1999
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OH
t
OLZ
t
ACS
t
CLZ
t
OHZ
Don't
care.
CS
Dout
Data Valid
t
CHZ
Write Cycle No.1 Timing Waveform
t
WC
Address
t
WR
OE
t
AS
t
AW
t
CW
(6)
CS
Don't
Care
WE
t
OHZ
t
WP
High-Z
t
DW
t
DH
t
OW
Dout
High-Z
Din
5
