TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
2M x 8 SRAM MODULE
SYS82000FKXA - 55/70/85/10/12
Elm Road, West Chirton Industrial Estate, North Shields,
NE29 8SE, ENGLAND. TEL +44 (0191) 2930500. FAX +44 (0191)
2590997
Issue 1.2 : January 1999
Features
•
Access Times of 55/70/85/100/120 ns.
•
36 Pin DIP Evolutionary Pinout.
•
5 Volt Supply ± 10%.
•
Low Power Dissipation:
Operating (min cycle)
605mW (Max).
Standby (
-L Version CMOS
) 2.64mW (Max).
•
Completely Static Operation.
•
Low Voltage V
CC
Data Retention.
•
On-board Supply Decoupling Capacitors.
•
Equivalent to EDI EDI8F82045C module.
Description
The SYS82000FKXA is a plastic 16Mbit Static
RAM Module housed in a standard 36 pin Dual In-
Line package organised as 2Mx8.
The module utilises 512Kx8 SRAM's housed in
TSOPII packages, and uses double sided surface
mount techniques, buried decoder and dual board
construction to achieve a very high density module.
The Evolutionary pinout provides an upgrade path
to 64Mbit.
Access times of 55 to 120 ns are available. The OE
pin allows faster access times than address access
during a read cycle.
Block Diagram
A0 - A18
D0 - D7
WE
OE
Pin Definition
NC
A19
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
TOP VIEW
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VCC
A20
NC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
512K X 8
SRAM
CS
512K X 8
SRAM
CS
512K X 8
SRAM
CS
512K X 8
SRAM
CS
CS
A19
A20
DECODER
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Power (+5V)
Ground
A0 - A20
D0 - D7
CS
WE
OE
V
CC
GND
Package Details
Plastic 36 Pin 0.6" Dual-In-Line low
profile Package.(DIP)
ISSUE 1.2 January 1999
SYS82000FKXA - 55/70/85/10/12
DC OPERATING CONDITIONS
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
(1)
Symbol
V
T(2)
P
T
T
STG
Min
-0.3
-
-55
Typ
-
1.0
-
Max
7.0
-
125
Unit
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) V
T
can be -3.0V pulse of less than 30ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial)
(Industrial)
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
4.5
2.2
-0.3
0
-40
Typ
5.0
-
-
-
-
Max
5.5
Vcc+0.3
0.8
70
85
Unit
V
V
V
o
C
o
C
DC Electrical Characteristics
(V
CC
=5V±10%)
Parameter
I/P Leakage Current
Address,OE,WE
T
A
0 to 70
o
C
Min Typ
-5
-5
-
-
-
-
-
2.4
-
-
-
-
-
-
-
-
max
5
5
109
12
480
280
0.4
-
Unit
µA
µA
mA
mA
mA
mA
V
V
Symbol Test Condition
I
LI
I
LO
I
CC1
TTL levels
CMOS levels
-L Version (CMOS)
0V < V
IN
< V
CC
CS = V
IH,
V
I/O
= GND to V
CC
, OE=V
IH
Min. Cycle, CS = V
IL
,V
IL
<V
IN
<V
IH
CS = V
IH
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
Output Leakage Current
Operating Supply Current
Standby Supply Current
I
SB1
I
SB2
I
SB3
V
OL
V
OH
Output Voltage
Typical values are at V
CC
=5.0V,T
A
=25
o
C and specified loading.
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Parameter
Input Capacitance
(Address,OE,WE)
I/P Capacitance
(other)
I/O Capacitance
C
IN1
C
IN2
C
I/O
Note: Capacitance calculated, not measured.
Symbol Test Condition
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
max
38
10
32
Unit
pF
pF
pF
2
SYS82000FKXA - 55/70/85/10/12
ISSUE 1.2 January 1999
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
I/O Pin
645
Ω
1.76V
100pF
Operation Truth Table
CS
H
L
L
L
L
OE
X
L
H
L
H
WE
X
H
L
L
H
DATA PINS
High Impedance
Data Out
Data In
Data In
High-Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
, I
SB3
I
CC1
I
CC1
I
CC1
I
SB1
, I
SB2
, I
SB3
MODE
Standby
Read
Write
Write
High-Z
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
Low V
cc
Data Retention Characteristics - L Version Only
Parameter
Symbol
Test Condition
min
typ
(1)
-
-
-
-
max
-
280
-
-
Unit
V
mA
ns
ms
V
DR
V
CC
for Data Retention
Data Retention Current
I
CCDR1
Chip Deselect to Data Retention Time t
CDR
Operation Recovery Time
t
R
Notes
CS > V
CC
-0.2V
2.0
2.0 < Vcc < 5.5V,CS>Vcc-0.2 -
See Retention Waveform
0
See Retention Waveform
5
(1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
3
ISSUE 1.2 January 1999
SYS82000FKXA - 55/70/85/10/12
AC OPERATING CONDITIONS
Read Cycle
-55
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
55
-
-
-
10
10
5
0
0
max
-
55
55
30
-
-
-
20
20
-70
min
70
-
-
-
10
10
5
0
0
max
-
70
70
40
-
-
-
25
25
-85
min
85
-
-
-
10
10
5
0
0
max
-
85
85
45
-
-
-
30
30
-10
min
100
-
-
-
10
10
5
0
0
max
-
100
100
50
-
-
-
35
35
-12
min
120
-
-
-
10
10
5
0
0
max Unit
-
120
120
55
-
-
-
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-55
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from End of Write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
55
50
50
0
40
5
0
25
0
5
max
-
-
-
-
-
-
20
-
-
-
-70
min
70
60
60
0
50
5
0
30
0
5
max
-
-
-
-
-
-
25
-
-
-
-85
min
85
70
70
0
60
5
0
35
0
5
max
-
-
-
-
-
-
30
-
-
-
-10
min
100
80
85
0
70
5
0
40
0
5
max
-
-
-
-
-
-
35
-
-
-
-12
min
120
100
100
0
80
5
0
45
0
5
max Unit
-
-
-
-
-
-
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note :
55ns not available over Industrial Temperature Range
4
SYS82000FKXA - 55/70/85/10/12
ISSUE 1.2 January 1999
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are
not referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
DH
t
OW
(8)
Dout
High-Z
Din
Data Valid
5
