T6B66BFG
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6B66BFG
ROW DRIVER LSI FOR DOT MATRIX LCD
The T6B66BFG is a row (common) driver LSI for a small- or
medium-scale dot matrix LCD.
The T6B66BFG generates timing signals for the display using
an on-chip oscillator and also controls the T6B65AFG column
(segment) LCD driver.
Four duty options are available: 1/17, 1/33, 1/49 and 1/65.
The IC is equipped with 65 low-impedance row-driver outputs.
Moreover, the IC incorporates internal resistors to divide the bias
voltage, a power supply operational amplifier, DC-DC converter
and a contrast control circuit; it is therefore easy to construct a
low-power LCD system consisting of a T6B66BFG and a
T6B65AFG column (segment) LCD driver.
T6B66BFG is lead (Pb)-free product.
QFP100-P-1420-0.65Q
Weight: 1.6 g (typ.)
Features
Row signal for LCD
65 low-impedance LCD driver outputs
On-chip oscillator with external resistor and internal capacitor
Duty
: 1/17, 1/33, 1/49, 1/65
Low power consumption
Logic power supply : 2.7 to 5.5 V
LCD power supply : V
DD
−
4.0 to V
DD
−
16.0 V
CMOS Si-Gate process
100-pin plastic flat package
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T6B66BFG
Block Diagram
*: When external clock operation is used, the clock should be input to OSC1.
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T6B66BFG
Pin Assignment
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T6B66BFG
Pin Functions
Pin Name
COM1 to COM65
CL
PM
/φ
/ LE
/ WR
DB0 to DB5
Pin No.
8 to 72
99
100
3
89
88
92 to 97
I/O
Output
Output
Output
Output
Input
Input
Input
Row driver outputs
Shift clock pulse for T6B65AFG
Pre-Frame signal for T6B65AFG
Clock signal for T6B65AFG
Latch Enable signal
Write Enable signal
Data bus
Display duty select
Display Duty
DS1
DS2
Frequency select
FS1
FS1, FS2
6, 7
Input
0
1
0
1
/ STB
/ RST
OSC1, OSC2
V
OUT1
V
OUT2
CnA to CnB
V
DD
, V
SS
V
LC1
to V
LC5
V
EE
87
91
1, 2
82
79
85, 86, 83,
84, 80, 81
90, 98
73 to 77
78
Input
Input
Input
Output
Output
―
―
―
―
FS2
0
0
1
1
f
OSC
(kHz)
26.88
53.76
215.0
430.1
f
PM
(Hz)
35
35
35
35
f /
φ
(kHz)
13.44
26.88
107.5
215.0
1 / 17
0
0
1 / 33
1
0
1 / 49
0
1
1 / 65
1
1
Functions
DS1, DS2
4, 5
Input
Standby pin: When / STB = L, all clocks stop.
Reset signal pin: When / RST = L, registers are cleared.
When using the internal clock oscillator, connect a resistor or ceramic oscillator
between OSC1 and OSC2.
When using an external clock, connect the clock to OSC1 and leave OSC2 open.
DC−DC output pin
DC−DC output pin
Connect using a capacitor for the DC−DC converter (n = 1 to 3)
Power supply
Power supply for the LCD drive
Power supply for the LCD drive
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T6B66BFG
Function of Each Block
●
Oscillator
The T6B66BFG has an on-chip oscillator with one external resistor.
Relation between oscillation frequency and R
f
R
f
51 kΩ
110 kΩ
460 kΩ
1100 kΩ
f
OSC
430 kHz
215 kHz
54 kHz
27 kHz
FS1
H
L
H
L
FS2
H
H
L
L
Note: The resistance values are typical values.
The oscillation frequency depends on how the
device is mounted. It is necessary to adjust the
oscillation frequency to a target value.
●
Timing generation circuit
This circuit divides the signals from the oscillator and generates display timing signals (CL, PM) and the
operating clock ( /
φ)
signal.
●
Shift register
65-bit shift register
●
DC-DC converter
(tripler and quadrupler)
The T6B66BFG has an on-chip DC-DC tripler and quadrupler. When / STB = L, VOUT1 and VOUT2 = VDD.
A 2.2 to 10-µF capacitor is recommended for this DC-DC Converter.
Quadrupler mode
Tripler mode
When not using the DC-DC converter, leave the CnA, CnB and V
OUTn
pins open and connect an external
V
EE
supply.
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