T89C51RD2
0 to 40MHz Flash Programmable 8-bit Microcontroller
1. Description
TEMIC T89C51RD2 is high performance CMOS Flash
version of the 80C51 CMOS single chip 8-bit
microcontroller. It contains a 64 Kbytes Flash memory
block for program and for data.
The 64 Kbytes Flash memory can be programmed either
in parallel mode or in serial mode with the ISP capability
or with software. The programming voltage is internally
generated from the standard V
CC
pin.
The T89C51RD2 retains all features of the TEMIC
80C52 with 256 bytes of internal RAM, a 7-source 4-
level interrupt controller and three timer/counters.
In addition, the T89C51RD2 has a Programmable
Counter Array, an XRAM of 1024 bytes, an EEPROM
of 2048 bytes, a Hardware Watchdog Timer, a more
versatile serial channel that facilitates multiprocessor
communication (EUART) and a speed improvement
mechanism (X2 mode). Pinout is either the standard 40/
44 pins of the C52 or an extended version with 6 ports
in a 64/68 pins package.
The fully static design of the T89C51RD2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T89C51RD2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
The added features of the T89C51RD2 makes it more
powerful for applications that need
pulse width
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
readers.
2. Features
•
80C52 Compatible
•
8051 pin and instruction compatible
•
Four 8-bit I/O ports (or 6 in 64/68 pins packages)
•
Three 16-bit timer/counters
•
256 bytes scratch pad RAM
•
7 Interrupt sources with 4 priority levels
•
ISP (In System Programming) using standard V
CC
power supply.
•
Dual Data Pointer
•
Variable length MOVX for slow RAM/peripherals
•
Improved X2 mode with independant selection for
CPU and each peripheral
•
2 k bytes EEPROM block for data storage
•
100K Write cycle
•
Programmable Counter Array with:
•
High Speed Output,
•
Compare / Capture,
•
Pulse Width Modulator,
•
Watchdog Timer Capabilities
•
Asynchronous port reset
•
Boot
FLASH contains low level FLASH
programming routines and a default serial loader
•
High-Speed Architecture
•
40 MHz in standard mode
•
20 MHz in X2 mode (6 clocks/machine cycle)
•
64K bytes on-chip Flash program / data Memory
•
Byte and page (128 bytes) erase and write
•
10k write cycles
•
On-chip 1024 bytes expanded RAM (XRAM)
•
Software selectable size (0, 256, 512, 768, 1024
bytes)
•
768 bytes selected at reset for T87C51RD2
compatibility
Rev. B - Fev. 18, 2000
•
Full duplex Enhanced UART
•
Low EMI (inhibit ALE)
•
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
•
Power control modes:
•
Idle Mode.
•
Power-down mode.
•
Power-off Flag.
1
Preliminary
T89C51RD2
•
Power supply: 5V +/- 10% or 3V – 10,+20% (Metal option)
•
Temperature ranges: Commercial (0 to +70C) and industrial (-40 to +85C).
•
Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64
Table 1. Memory Size
PDIL40
PLCC44
VQFP44 1.4
T89C51RD2
64k
2k
1024
1280
32
Flash (bytes)
EEPROM (bytes)
XRAM (bytes)
TOTAL RAM
(bytes)
I/O
PLCC68
Flash (bytes)
VQFP64 1.4
T89C51RD2
64k
EEPROM
(bytes)
2k
XRAM (bytes)
1024
TOTAL RAM
(bytes)
1280
I/O
48
3. Block Diagram
T2EX
PCA
RxD
TxD
V
CC
ECI
Vss
(3) (3)
XTAL1
XTAL2
ALE/ PROG
PSEN
CPU
EA
RD
WR
(3)
(3)
Timer 0
Timer 1
INT
Ctrl
Parallel I/O Ports & Ext. Bus
EUART
RAM
256x8
(1)
(1) (1)
(1)
Flash
64Kx8
XRAM
1Kx8
EEPROM
2Kx8
PCA
Timer2
C51
CORE
IB-bus
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5
(2)
(2)
Watch
Dog
(3) (3)
RESET
T0
T1
(3) (3)
P1
P2
P3
P4
INT0
INT1
P0
P5
(1): Alternate function of Port 1
(2): Only available on high pin count packages
(3): Alternate function of Port 3
2
Rev. B - Fev. 18, 2000
Preliminary
T2
T89C51RD2
4. SFR Mapping
The Special Function Registers (SFRs) of the T89C51RD2 fall into the following categories:
•
•
•
•
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
I/O port registers: P0, P1, P2, P3. P4, P5
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
Power and clock control registers: PCON
•
Hardware Watchdog Timer register: WDTRST, WDTPRG
•
Interrupt system registers: IE, IP, IPH
•
Flash and EEPROM registers: FCON, EECON, EETIM
•
Others: AUXR, AUXR1; CKCON
Table below shows all SFRs with their address and their reset value.
Bit
address-
able
0/8
1/9
2/A
3/B
Non Bit addressable
4/C
5/D
6/E
7/F
F8h
F0h
E8h
B
0000 0000
P5 bit
addressable
1111 1111
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
T2CON
0000 0000
P4 bit
addressable
1111 1111
IP
X000 000
P3
1111 1111
IE
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8
CH
0000 0000
CCAP0H
CCAP1H
CCAPL2H
CCAPL3H
CCAPL4H
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
FFh
F7h
CL
0000 0000
CCAP0L
CCAP1L
CCAPL2L
CCAPL3L
CCAPL4L
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
EFh
E0h
D8h
D0h
C8h
C0h
E7h
CMOD
CCAPM0
00XX X000
X000 0000
FCON*
EECON
XXXX 0000 XXXX XX00
T2MOD
RCAP2L
XXXX XX00
0000 0000
CCAPM1
X000 0000
EETIM
0000 0000
RCAP2H
0000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
DFh
D7h
TL2
0000 0000
TH2
0000 0000
P5 byte
addressable
1111 1111
SADEN
0000 0000
IPH
X000 0000
SADDR
0000 0000
AUXR1
XXXX 00X0
SBUF
XXXX XXXX
WDTRST
WDTPRG
XXXX XXXX XXXX X000
CFh
C7h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
BFh
B7h
AFh
A7h
9Fh
97h
TMOD
0000 0000
SP
0000 0111
1/9
TL0
0000 0000
DPL
0000 0000
2/A
TL1
0000 0000
DPH
0000 0000
3/B
TH0
0000 0000
TH1
0000 0000
AUXR
XX0X 1000
CKCON
X000 0000
PCON
00X1 0000
7/F
8Fh
87h
4/C
5/D
6/E
Rev. B - Fev. 18, 2000
3
Preliminary
T89C51RD2
reserved
FCON access is reserved for the Flash API and ISP software.
4
Rev. B - Fev. 18, 2000
Preliminary
T89C51RD2
5. Pin Configuration
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7CEX4
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0/AD0
P1.4/CEX1
P1.3/CEX0
VSS1/NIC*
P1.1/T2EX
P0.2/AD2
P0.3/AD3
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR
P2.2/A10
P2.3/A11
P2.4/A12
P3.7/RD
NIC*
P2.0/A8
P2.1/A9
XTAL2
XTAL1
VSS
P0.0/AD0
P0.1/AD1
P1.2/ECI
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE/PROG
PSEN
P2.7/AD15
P2.6/AD14
P2.5/AD13
P2.4/AD12
P2.3/AD11
P2.2/AD10
P2.1/AD9
P2.0/AD8
P1.5/CEX2
P1.6/CEX3
P1.7/CEx4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2 1 44 43 42 41 40
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.0/T2
PDIL
PLCC
P1.4/CEX1
P1.3/CEX0
VSS1/NIC*
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43 42 41 40 39 38 37 36 35 34
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
VQFP44 1.4
12 13 14 15 16 17 18 19 20 21 22
P2.3/A11
P2.4/A12
NIC*
P2.0/A8
XTAL1
P2.2/A10
P3.6/WR
P3.7/RD
P2.1/A9
XTAL2
VSS
*NIC: No Internal Connection
Rev. B - Fev. 18, 2000
P0.3/AD3
P1.2/ECI
P1.0/T2
VCC
VCC
5
Preliminary
