TB62705CPG/CFG/CFNG
TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TB62705CPG, TB62705CFG, TB62705CFNG
8-BIT SHIFT REGISTER, LATCHES & CONSTANT-CURRENT DRIVERS
The TB62705CPG / CFG / CFNG are specifically designed for
LED and LED DISPLAY constant-current drivers.
These constant-current output circuits can support the set-up of
an external resistor (I
OUT
= 5~90mA).
This I
C
is a monolithic integrated circuit designed to be used
together with Bi-CMOS process.
The devices consist of an 8-bit shift register, latch, AND-GATE
and constant-current drivers.
This devices are a product for the Pb free(Sn-Ag).
TB62705CPG
FEATURES
Constant-current Output
: current with one resistor for
5 to 90mA.
TB62705CFG
Maximum Clock Frequency : f
CLK
= 15 (MHz)
(Cascade Connecte Operate,
Topr = 25°C)
5V C−MOS Compatible Input
Package
: DIP16−P−300−2.54A (TB62705CPG)
SSOP16−P−225−1.00A (TB62705CFG)
SSOP16−P−225−0.65B (TB62705CFNG)
TB62705CFNG
Constant Output Current Matching:
OUTPUT-GND
VOLTAGE
≥
0.4 V
≥
0.7 V
CURRENT
MATCHING
±6.0%
±6.0%
OUTPUT
CURRENT
5~40 mA
5~90 mA
PIN CONNECTION
(Top view)
Weight
DIP16−P−300−2.54A
: 1.11 g (typ.)
SSOP16−P−225−1.00A : 0.14 g (typ.)
SSOP16−P−225−0.65B : 0.07 g (typ.)
V
DD
R-EXT
SERIAL-OUT
GND
SERIAL-IN
CLOCK
LATCH
OUTn
OUTn
OUTn
OUTn
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ENABLE
OUTn
OUTn
OUTn
OUTn
Company Headquarters
3 Northway Lane North
Latham,
New York
12110
Toll Free: 800.984.5337
Fax:
518.785.4725
Web: www.marktechopto.com | Email: info@marktechopto.com
California Sales Office:
950 South Coast Drive, Suite 225
265
Costa Mesa, California 92626
Toll Free: 800.984.5337
Fax: 714.850.9314
TB62705CPG/CFG/CFNG
BLOCK DIAGRAM
OUTn
OUTn
OUTn
TIMING DIAGRAM
CLOCK
5V
0V
5V
0V
5V
0V
5V
0V
Off
On
Off
On
Off
On
Off
5V
0V
SERIAL-IN
LATCH
ENABLE
OUT0
OUT1
OUT3
OUT7
SERIAL-OUT
Note:
Latches are level-sensitive, not rising edge-sensitive, and are not synchronized with the CLOCK signal. The
data will pass through the latch circuit if the latch input is set at “H” level, and will be retained if the input is
set at “L”.
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2005-10-06
TB62705CPG/CFG/CFNG
PIN DESCRIPTION
PIN No.
1
2
3
4
5~12
13
14
15
16
PIN NAME
GND
SERIAL−IN
CLOCK
LATCH
OUTn
ENABLE
SERIAL−OUT
R−EXT
V
DD
GND terminal for control logic
Input pin for shift register serial data
Clock input terminal for data shift to up-edge.
Data strobe input terminal. Latches pass LATCH data with “H” level input and retain data with “L”
level input.
Output terminals
Input terminal for output enable. All outputs ( OUTn ) go off with ENABLE data input at "H" level
and go on with data input at "L" level.
Output terminal for serial data for the next SERIAL-IN terminal.
Input terminal for connecting a resistor to regulate all output currents.
5-V supply pin of the IC
FUNCTION
TRUTH TABLE
CLOCK
UP
UP
UP
DOWN
DOWN
LATCH
H
L
H
X
X
ENABLE
L
L
L
L
H
SERIAL−IN
D
n
D
n+1
D
n+2
D
n+3
D
n+3
OUTn
D
n
··· D
n−5
··· D
n−7
No change
D
n+2
··· D
n−3
··· D
n−5
D
n+2
··· D
n−3
··· D
n−5
Off
SERIAL−OUT
D
n−7
D
n−6
D
n−5
D
n−5
D
n−5
Note:
OUTn = on if D
n
= H level, and OUTn = off if D
n
= L level.
An external resistor is connected with R−EXT and GND. Be sure to administer the correct power supply
voltage.
INPUT/OUTPUT EQUIVALENT CIRCUITS
1.
ENABLE
terminal
2.
LATCH
terminal
3. CLOCK, SERIAL−IN terminal
4. SERIAL−OUT terminal
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2005-10-06
TB62705CPG/CFG/CFNG
MAXIMUM RATINGS
(Ta = 25°C)
CHARACTERISTIC
Supply Voltage
Input Voltage
Output Current
Output Voltage
Clock Frequency
GND Terminal Current
Power Dissipation
SYMBOL
V
DD
V
IN
I
OUT
V
CE
f
CK
I
GND
P
D
RATING
0~7.0
−0.4~V
DD
+ 0.4
90
−0.5~17.0
15
720
1.47 (CPG−type : FREE AIR, Ta = 25°C)
0.78 (CFG / CFNG−type : ON PCB, Ta = 25°C)
85 (CPG−type : FREE AIR, Ta = 25°C)
160 (CFG / CFNG−type : ON PCB, Ta = 25°C)
−40~85
−55~150
UNIT
V
V
mA
V
MHz
mA
W
Thermal Resistance
Operating Temperature
Storage Temperature
R
th (j−a)
T
opr
T
stg
°C / W
°C
°C
Note:
CPG type: For an ambient temperature above 25°C, the derating is 11.8 mW/°C.
CFG and CFNG type: For an ambient temperature above 25°C, the derating is 6.3 mW/°C.
RECOMMENDED OPERATING CONDITION
(Ta =
−
40~85°C unless otherwise stated)
CHARACTERISTIC
Supply Voltage
Output Voltage
SYMBOL
V
DD
V
OUT
I
O
Output Current
I
OH
I
OL
V
IH
Input Voltage
V
IL
LATCH Pulse Width
CLOCK Pulse Width
ENABLE Pulse Width
Set-up Time for DATA
Hold Time for DATA
Set-up Time for LATCH
Hold Time for LATCH
Clock Frequency
t
w LAT
t
w CLK
t
w EN
t
setup (D)
t
hold (D)
t
setup (L)
t
hold (L)
f
CK
Cascade operation
Ta = 85°C
(CPG−type FREE AIR)
Ta = 85°C
(CFG / CFNG−type ON PCB)
V
DD
= 4.5~5.5 V
―
CONDITION
―
―
OUTn , DC 1 circuit
SERIAL−OUT
SERIAL−OUT
―
MIN
4.5
―
5
―
―
0.7
V
DD
−0.3
100
50
4500
60
20
100
60
10.0
―
―
TYP.
5.0
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
MAX
5.5
15.0
88
1.0
−1.0
V
DD
+0.3
0.3
V
DD
―
―
―
―
―
―
―
―
0.82
W
0.40
mA
UNIT
V
V
V
ns
ns
ns
ns
ns
ns
ns
MHz
Power Dissipation
P
D
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2005-10-06
TB62705CPG/CFG/CFNG
ELECTRICAL CHARACTERISTICS
(V
DD
= 5.0 V, Ta = 25°C unless otherwise stated)
CHARACTERISTIC
"H" Level
Input Voltage
"L" Level
Output Leakage Current
Output Voltage
S−OUT
V
IL
I
OH
V
OL
V
OH
I
OL1
I
OL2
Current Skew
Output Current 2
Current Skew
Supply Voltage Regulation
Pull−Up Resistor
Pull−Down Resistor
∆I
OL1
I
OL3
I
OL4
∆I
OL2
% / V
DD
R
IN (up)
R
IN (down)
I
DD (off) 1
"OFF"
Supply Current
"ON"
I
DD (off) 2
I
DD (off) 3
I
DD (on) 1
I
DD (on) 2
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
V
OH
= 15.0 V
I
OL
= 1.0 mA
I
OH
=
−1.0
mA
V
CE
= 0.7 V
V
CE
= 0.4 V
I
O
= 40 mA,
VCE = 0.4 V
V
CE
= 1.0 V
V
CE
= 0.7 V
I
O
= 75 mA,
V
CE
= 0.7 V
R
EXT
= 470
Ω
(Include skew)
R
EXT
= 470
Ω
R
EXT
= 250
Ω
(Include skew)
R
EXT
= 250
Ω
―
SYMBOL
V
IH
TEST
CIR−
CUIT
―
CONDITION
―
MIN
0.7
V
DD
GND
―
―
4.6
34.1
33.7
―
64.2
63.8
―
―
150
100
―
3.5
6.5
7.0
10.0
TYP.
―
―
―
―
―
40.0
39.5
±1.5
75.5
75.0
±1.5
1.5
300
200
0.6
5.8
10.7
12.0
22.0
MAX
V
DD
0.3
V
DD
10
0.4
―
45.9
45.3
±6.0
86.8
86.2
±6.0
5.0
600
400
1.2
8.0
15.0
18.0
32.0
mA
V
UNIT
µA
V
Output Current 1
mA
%
mA
%
%/V
kΩ
kΩ
R
EXT
= 470
Ω,
Ta =
−40~85°C
―
―
R
EXT
= OPEN, OUT0 ~ 7 = off
R
EXT
= 470
Ω,
OUT0 ~ 7 = off
R
EXT
= 250
Ω,
OUT0 ~ 7 = off
R
EXT
= 470
Ω,
OUT0 ~ 7 = on
R
EXT
= 250
Ω,
OUT0 ~ 7 = on
5
2005-10-06
