SRC9000 Series
High Reliability Tantalum Capacitors for Space Applications
AVX SRC9000 microminiature capacitors are designed and built to meet the high
reliability and long term requirements of military space applications. All SRC9000
capacitors meet all of the requirements of Mil-PRF-55365 and include DPA
requirements per MIL-STD-1580. SRC9000 establishes a rigorous screening test
schedule designed to detect and eliminate from shipment any capacitor or capacitor
test lots that exhibits poor performance or reliability. SRC9000 establishes a
continuous test schedule to determine baseline reliability data for specific product
shipped under this specification. SRC9000 assures that proper lot control and lot
traceability procedures are in effect.
HOW TO ORDER
D
Type
(3 letters)
TBJ
TAZ
Case
Size
227
Capacitance
Code
*
006
C
Standard or
Low ESR
Range
C = Std ESR
L = Low ESR
#@
Packaging
Qualification/
Reliability
B = Bulk
# = Inspection Level
R = 7" T&R
S = 13" T&R S = Std. Conformance
L = Group A
@ = Failure Rate Level
Weibull:
B = 0.1%/1000 hrs,
90% conf.
C = 0.01%/1000 hrs,
90% conf.
D = 0.001%/1000 hrs,
90% conf.
Comm: Z = Non ER
90
Termination
Finish
90 = SRC9000
++
Surge Test
Option
00 = None
23 = 10 cycles,
+25°C
24 = 10 cycles,
-55°C &
+85°C
45 = 10 cycles,
-55ºC &
+85ºC
before
Weibull
Capacitance
Voltage
Tolerance
Code
M = ±20% 004 = 4Vdc
K = ±10% 006 = 6Vdc
J = ±5%
010 = 10Vdc
015 = 15Vdc
(TAZ)
016 = 16Vdc
(TBJ)
020 = 20Vdc
025 = 25Vdc
035 = 35Vdc
050 = 50Vdc
CAPACITANCE AND RATED VOLTAGE, V
R
(VOLTAGE CODE) RANGE
(LETTER DENOTES CASE SIZE)
Capacitance
µF
0.1
0.15
0.22
0.33
0.47
0.68
1
1.5
2.2
3.3
4.7
6.8
10
15
22
33
47
68
100
150
220
330
470
680
Code
104
154
224
334
474
684
105
155
225
335
475
685
106
156
226
336
476
686
107
157
227
337
477
687
4V
TAZ TBJ
6V
TAZ
TBJ
Voltage Rating DC (V
R
) to 85°C
10V
15V/16V
20V
25V
TAZ TBJ TAZ TBJ TAZ TBJ TAZ TBJ
35V
TAZ TBJ
A
A
A
A
A
(M)
/B
A
(M)
/B
A/B
A/B/C
B/C
B/C
B/C/D
C/D
C/D
C/D
D/E
D
(M)
50V
TAZ TBJ
A
A
B
B
C
D
E
F
F
G
H
A
A
(M)
/B
A
(M)
/B
B
C
C
C
C/D
D
D
D
D
A
A
A
A/B
A
A/C
A/B
B/D
A/B
B/E
A/B
B/D
A
D/E/F A/B/C
E
B
E/G
C/D
F/H B/C/D
G
H
D
H
E
H
A
A
A/B
A
A/C
A/B
B/D
A/B
B/E
A/B
B/D/E A/B/C
D/E/F A/B/C
E
B/C
F/G
C/D
F/G/H B/C/D
G
C/D
G
D
H
C/D
H
E
(M)
E /V
A
A
A
A
A
A
A
A/B
A
A/B
A
A/C
A/B
A/C
A/B
B/D
A/B
B/C/D A/B B/C/D/E A/B
B/C/D/E A/B
D/E
A/B/C
B/C/D/E A/B/C D/E/F
B/C
D/E/F A/B/C
E/F
B/C
E
B/C
F/G
B/C/D
F/G B/C/D F/G/H
C/D
F/G/H C/D
G/H
C/D
G
C/D
G/H
D
G/H
C/D
H
D/E
H/X
D
D
(M)
/V
(M)
/E
H
D
V
D
(M)
/E
E
(M)
/V
A
A
A/B
A/B
B/C
B/D
D/E
E
E/F
E/F
F/G
G/H
H
H/X
A
A
A
A
A
A
B
A/B
A
B/C
A/B
A/B
D
A/B
B
D/E
A/B/C
B
E
B/C
A/B/C
F
B/C
B/C
F/G
B/C/D
B/C
G
C/D
B/C/D G/H
D
C/D G/H/X C/D
C/D
H/X
D/E
D
D
(M)
D/E
V
V
A
A
B
C
D
E
F
G
G/H
H
X
19
FPGA/CPLD