TC1025
Linear Building Block – Dual Low - Power Comparator
FEATURES
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Rail-to-Rail Inputs and Outputs
Optimized for Single-Supply Operation
Small Package ..........................................................
8-Pin MSOP (Consumes Only Half the Space of an
8-Pin SOIC), 8-Pin SOIC, 8-Pin DIP
Ultra Low Input Bias Current ..... Less than 100 pA
Low Quiescent Current ........................ 8
µ
A (Typ.)
Operates Down to V
DD
= 1.8V
GENERAL DESCRIPTION
The TC1025 is a dual low-power comparator with a
typical supply current of 8µA and operation guaranteed to
V
DD
= 1.8V. Input and output signal swing is rail-to-rail.
Available in a space-saving 8-pin MSOP package, the
TC1025 consumes half the board area required by a stan-
dard 8-pin SOIC package. It also is available in 8-pin SOIC
and DIP packages. It is ideal for applications requiring high
integration, small size and low power.
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s
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APPLICATIONS
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Power Management Circuits
Battery Operated Equipment
Consumer Products
ORDERING INFORMATION
Part No.
TC1025CEPA
TC1025CEUA
TC1025CEOA
Package
8-Pin DIP
8-Pin MSOP
8-Pin SOIC
Temperature
Range
– 40°C to +85°C
– 40°C to +85°C
– 40°C to +85°C
FUNCTIONAL BLOCK DIAGRAM
TC1043EV Evaluation Kit for Linear Building Block Family
OUTA
TC1025
OUTB
V
SS
A
–
–
B
V
DD
+
INA+
+
INB+
INA–
INB–
PIN CONFIGURATIONS
(MSOP, DIP, and SOIC)
OUTA
V
SS
INA+
INA–
1
2
3
4
TC1025_EPA
TC1025_EUA
TC1025_EOA
8
7
6
5
OUTB
V
DD
INB+
INB–
2001 Microchip Technology Inc.
DS21366A
TC1025-1 1/04/01
Linear Building Block-
Dual Low-Power Comparator
TC1025
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage ...........................................................6.0V
Voltage on Any Pin:
(With Respect to Supplies) .. (V
SS
– 0.3V) to (V
DD
+0.3V)
Operating Temperature Range: ............. – 40°C to + 85°C
Storage Temperature Range ................ – 55°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +260°C
* Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS:
Typical values apply at 25°C and V
DD
= 3.0V. Minimum and maximum
values apply for T
A
= –40° to +85°C,and V
DD
= 1.8V to 5.5V, unless otherwise specified.
Symbol
V
DD
I
Q
V
ICMR
V
OS
I
B
V
OH
V
OL
CMRR
PSRR
I
SRC
Parameter
Supply Voltage
Supply Current
Test Conditions
All outputs unloaded
Min
1.8
—
V
SS
– 0.2
–5
–5
—
V
DD
– 0.3
—
66
60
1
Typ
—
8
—
—
—
—
—
—
—
—
Max
5.5
12
V
DD
+0.2
+5
+5
±100
—
0.3
—
—
—
Unit
V
µA
V
mV
mV
pA
V
V
dB
dB
mA
Comparator
Common Mode Input Voltage Range
Input Offset Voltage
V
DD
= 3V, V
CM
=1.5V, T
A
= 25°C
T
A
= –40°C to 85°C
Input Bias Current
T
A
= 25°C, IN+, IN– = V
DD
to V
SS
Output High Voltage
R
L
= 10KΩ to V
SS
Output Low Voltage
R
L
= 10KΩ to V
DD
Common Mode Rejection Ratio
T
A
= 25°C, V
DD
= 5V
V
CM
= V
DD
to V
SS
Power Supply Rejection Ratio
T
A
= 25°C, V
CM
=1.2V
V
DD
= 1.8V to 5V
Output Source Current
IN+ = V
DD,
IN– = V
SS
Output Shorted to V
SS
V
DD
= 1.8V
Output Sink Current
IN+ = V
SS,
IN_ = V
DD,
Output Shorted to V
DD
V
DD
= 1.8V
Response Time
100 mV Overdrive,C
L
= 100pF
Response Time
10 mV Overdrive, C
L
= 100pF
I
SINK
2
—
—
mA
t
PD1
t
PD2
—
—
4
6
—
—
µsec
µsec
TC1025-1
1/04/01
2
2001 Microchip Technology Inc.
DS21366A
Linear Building Block-
Dual Low-Power Comparator
TC1025
DETAILED DESCRIPTION
The TC1025 is one of a series of very low-power, linear
building block products targeted at low-voltage, single-
supply applications. The TC1025 minimum operating volt-
age is 1.8V, and typical supply current is only 8
µA.
It
combines two comparators in a single package.
1
R
B
=
1
(
(VV * R )
)
– R
[
THR
R
A
A
– 1
R
C
]
Equation 2.
6. Verify the threshold voltages with these formulas:
V
SRC
rising:
Comparators
The TC1025 contains two comparators. The compara-
tors' input range extends beyond both supply voltages by
200mV and the outputs will swing to within several millivolts
of the supplies depending on the load current being driven.
The comparators exhibit propagation delay and supply
current which are largely independent of supply voltage. The
low input bias current and offset voltage make them suitable
for high impedance precision applications.
V
THR
=
(V
R
) (R
A
)
1
1
1
[(
R
)
+
(
R
)
+
(
R
) ]
A
B
C
Equation 3.
V
SRC
falling:
V
THF
= V
THR
–
*
[
(R R V )
]
A
DD
C
Equation 4.
TYPICAL APPLICATIONS
The TC1025 lends itself to a wide variety of applications,
particularly in battery-powered systems. Typically, it finds
application in power management, processor supervisory,
and interface circuitry.
32.768 KHz ‘Time Of Day Clock’ Crystal
Controlled Oscillator
A very stable oscillator driver can be designed by using
a crystal resonator as the feedback element. Figure 2 shows
a typical application circuit using this technique to develop a
clock driver for a Time Of Day (TOD) clock chip. The value
of R
A
and R
B
determine the DC voltage level at which the
comparator trips — in this case one-half of V
DD
. The RC time
constant of R
C
and C
A
should be set several times greater
than the crystal oscillator’s period, which will ensure a 50%
duty cycle by maintaining a DC voltage at the inverting
comparator input equal to the absolute average of the output
signal.
External Hysteresis (Comparator)
Hysteresis can be set externally with two resistors using
positive feedback techniques (see Figure 1). The design
procedure for setting external comparator hysteresis is as
follows:
1. Choose the feedback resistor R
C
. Since the input
bias current of the comparator is at most 100 pA, the current
through R
C
can be set to 100 nA (i.e. 1000 times the input
bias current) and retain excellent accuracy. The current
through R
C
at the comparator’s trip point is V
R
/ R
C
where V
R
is a stable reference voltage.
2. Determine the hysteresis voltage (V
HY
) between
the upper and lower thresholds.
3. Calculate R
A
as follows.
R
A
= R
C
Non-Retriggerable One Shot Multivibrator
Using two comparators, a non-retriggerable one shot
multivibrator can be designed using the circuit configuration
of Figure 3. A key feature of this design is that the pulse width
is independent of the magnitude of the supply voltage
because the charging voltage and the intercept voltage are
a fixed percentage of V
DD
. In addition, this one shot is
capable of pulse width with as much as a 99% duty cycle and
exhibits input lockout to ensure that the circuit will not re-
trigger before the output pulse has completely timed out.
The trigger level is the voltage required at the input to raise
the voltage at node A higher than the voltage at node B, and
is set by the resistive divider R4 and R10 and the impedance
network composed of R1, R2, and R3. When the one shot
has been triggered, the output of CMPTR2 is high, causing
the reference voltage at the non-inverting input of CMPTR1
to go to V
DD
. This prevents any additional input pulses from
disturbing the circuit until the output pulse has
timed out.
3
TC1025-1 1/04/01
(
V
)
V
HY
DD
Equation 1.
4. Choose the rising threshold voltage for V
SRC
(V
THR
).
5. Calculate R
B
as follows:
2001 Microchip Technology Inc.
DS21366A
Linear Building Block-
Dual Low-Power Comparator
TC1025
The value of the timing capacitor C1 must be small
enough to allow CMPTR1 to discharge C1 to a diode voltage
before the feedback signal from CMPTR2 (through R10)
switches CMPTR1 to its high state and allows C1 to start an
exponential charge through R5. Proper circuit action de-
pends upon rapidly discharging C1 through the voltage set
by R6, R9, and D2 to a final voltage of a small diode drop.
Two propagation delays after the voltage on C1 drops below
the level on the non-inverting input of CMPTR2, the output
of CMPTR1 switches to the positive rail and begins to charge
C1 through R5. The time delay which sets the output pulse
width results from C1 charging to the reference voltage set
by R6, R9, and D2, plus four comparator propagation
delays. When the voltage across C1 charges beyond the
reference, the output pulse returns to ground and the input
is again ready to accept a trigger signal.
V
DD
3
V
L
=
Equation 7.
Using the same resistors as before, capacitor C1 must
now discharge through R4 toward ground. The output will
return to a high state when the voltage across the capacitor
has discharged to a value equal to V
L
. The period of
oscillation will be twice the time it takes for the RC circuit to
charge up to one half its final value. The period can be
calculated from:
1
= 2 (0.694) (R4) (C1)
FREQ
Equation 8.
Oscillators and Pulse Width Modulators
Microchip’s linear building block comparators adapt well
to oscillator applications for low frequencies (less than 100
KHz). Figure 4 shows a symmetrical square wave generator
using a minimum number of components. The output is set
by the RC time constant of R4 and C1, and the total
hysteresis of the loop is set by R1, R2, and R3. The
maximum frequency of the oscillator is limited only by the
large signal propagation delay of the comparator in addition
to any capacitive loading at the output which degrades the
slew rate.
To analyze this circuit, assume that the output is initially
high. For this to occur, the voltage at the inverting input must
be less than the voltage at the non-inverting input. There-
fore, capacitor C1 is discharged. The voltage at the non-
inverting input (V
H
) is:
V
H
=
R2(V
DD
)
[R2 + (R1 || R3)]
The frequency stability of this circuit should only be a
function of the external component tolerances.
Figure 5 shows the circuit for a pulse width modulator
circuit. It is essentially the same as in Figure 4, but with the
addition of an input control voltage. When the input control
voltage is equal to one-half V
DD
, operation is basically the
same as described for the free-running oscillator. If the input
control voltage is moved above or below one-half V
DD
, the
duty cycle of the output square wave will be altered. This is
because the addition of the control voltage at the input has
now altered the trip points. The equations for these trip
points are shown in Figure 5 (see V
H
and V
L
).
Pulse width sensitivity to the input voltage variations can
be increased by reducing the value of R6 from 10 KΩ and
conversely, sensitivity will be reduced by increasing the
value of R6. The values of R1 and C1 can be varied to
produce the desired center frequency.
EVALUATION KIT
The TC1043EV consists of a four-inch by six-inch pre-
wired application circuit board. Pre-configured circuits in-
clude a pulse width modulator, wake-up timer, function
generator, and others. On-board current meter terminals,
voltage regulator, and a user-prototyping area speed circuit
development. Please contact your local Microchip Technol-
ogy representative for more information.
Equation 5.
where, if R1 = R2 = R3, then:
V
H
=
2 (V
DD
)
3
Equation 6.
Capacitor C1 will charge up through R4. When the
voltage at the comparator’s inverting input is equal to V
H
,
the comparator output will switch. With the output at ground
potential, the value at the non-inverting input terminal (V
L
) is
reduced by the hysteresis network to a value given by:
TC1025-1
1/04/01
4
2001 Microchip Technology Inc.
DS21366A
Linear Building Block-
Dual Low-Power Comparator
TC1025
R
C
TC1025
R
A
V
SRC
R
B
V
R
V
DD
R
A
150K
V
DD
32.768 KHz
V
DD
1/2 TC1025
TC1025
+
–
V
OUT
1/2 TC1025
R
B
150K
+
–
R
C
C
A
100 pF
1M
Tper = 30.52
µsec
V
OUT
Figure 1. Comparator External Hysteresis Configuration
V
DD
Figure 2. 32.768 KHz “Time of Day” Clock Oscillator
TC1025
R1
IN
R3
1M
A
R4
1M
–
100K
R2
100K
B
CMPTR1
R5
10M
R6
562K
C
R7
1M
TC1025
+
D1
R10
61.9K
C1
100 pF
R8
R9
243K
10M
–
CMPTR2
OUT
OUT
V
DD
GND
+
C
IN
t
0
GND
V
DD
GND
D2
Figure 3. Non-Retriggerable Multivibrator
V
DD
R1
100K
V
DD
TC1025
V
C
R4
V
DD
R6
10K
R1
100K
TC1025
R4
1/2 TC1025
V
DD
V
H
=
V
DD
(R1R2R6 + R2R3R6) + V
C
(R1R2R3)
R1R2R6 + R 1R3R6 + R 2R3R6 + R1R2R3
–
C1
1/2 TC1025
V
H
=
V
L
=
R2 (V
DD
)
R2 + (R1||R3)
C1
–
+
V
L
=
V
DD
(R2R3R6) + V
C
(R1R2R3)
R1R2R6 + R1R3R6 + R 2R3R6 + R1R2R3
1
2 (0.694) (R4) (C1)
+
FREQ =
R2
100K
R3
100K
(V
DD
) (R2||R3)
R1 + (R2||R3)
1
FREQ =
2(0.694)(R4)(C1)
R2
100K
R3
100K
For Square Wave Generation
Select R1 = R2 = R3
V
C
= V
DD
2
Figure 4. Square Wave Generation
2001 Microchip Technology Inc.
DS21366A
Figure 5. Pulse Width Modulator
5
TC1025-1 1/04/01
