TC1322
12-Bit Digital-to-Analog Converter with Two-Wire Interface
FEATURES
s
s
s
s
s
s
12-Bit Digital-Analog Converter
8-Pin SOIC and 8-Pin MSOP Packages
2.7–5.5V Single-Supply Operation
Simple SMBus/I
2
C Serial Interface
Low Power - 0.35mA Operation, 0.5
µ
A Shutdown
Guaranteed Monotonicity
GENERAL DESCRIPTION
The TC1322 is a serially accessible 12-bit voltage output
digital-to-analog converter (DAC). The DAC produces an
output voltage that ranges from ground to an externally
supplied reference voltage. It operates from a single power
supply that can range from 2.7V to 5.5V, making it ideal for a
wide range of applications. Built into the part is a power-on
reset function that ensures that the device starts at a known
condition.
Communication with the TC1322 is accomplished via a
simple 2-wire SMBus/I
2
C compatible serial port with the
TC1322 acting as a slave only device. The host can enable the
SHDN bit in the CONFIG register to activate the low-power
standby mode.
TYPICAL APPLICATIONS
s
s
s
s
Programmable Voltage Sources
Digital-Controlled Amplifiers/Attenuators
Process Monitoring and Control
Microprocessor- controlled systems
PIN CONFIGURATION
8-Pin MSOP
V
REF
1
SDA 2
SCL 3
GND 4
8
V
DD
ORDERING INFORMATION
Part No.
TC1322EOA
TC1322EUA
Package
Temp. Range
7 DAC-OUT
6 NC
5
VOUT
TC1322
8-Pin SOIC (Narrow) –40°C to +85°C
8-Pin MSOP
–40°C to +85°C
8-Pin SOIC (Narrow)
V
REF
SDA
SCL
GND
1
2
3
4
8
7
V
DD
DAC-OUT
NC
VOUT
TC1322
6
5
FUNCTIONAL BLOCK DIAGRAM
V
DD
Configuration Register
TC1322
SDA
SCL
Serial Port
Interface
Control
DAC–OUT
Data Register
DAC
V
OUT
V
REF
GND
TC1322-1
6/23/00
TelCom Semiconductor reserves the right to make changes in the circuitry and specifications of its devices.
12-Bit Digital-to-Analog Converter with
Two-Wire Interface
TC1322
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V
DD
) ................................................. +6V
Voltage On Any Pin ............ (GND – 0.3V) to (V
DD
+ 0.3V)
Operating Temperature (T
A
) ............................ See Below
Storage Temperature (T
STG
) ................. – 65°C to +150°C
Current On Any Pin ...............................................±50 mA
Package Thermal Resistance (θ
JA
) .................... 330°C/W
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS:
V
DD
= 2.7V to 5.5V, – 40°C
≤
T
A
≤
+85°C, unless otherwise noted.
Symbol
Parameter
Power Supply
V
DD
I
DD
I
DD-STANDBY
Supply Voltage
Operating Current
Standby Supply Current
Test Conditions
Min
2.7
—
—
Typ
—
0.35
0.1
Max
5.5
0.5
1
Unit
V
mA
µA
V
DD
= 5.5V, V
REF
= 1.2V
Serial Port Inactive (Note 1)
V
DD
=3.3V
Serial Port Inactive (Note 1)
STATIC PERFORMANCE–ANALOG SECTION:
(V
DD
= 2.7V to 5.5V, V
REF
= 1.2V, –40°C
≤
T
A
≤
85°C,
unless otherwise noted.)
Symbol
INL
FSE
DNL
V
OS
TCV
OS
PSRR
V
REF
I
REF
V
SW
R
OUT
I
OUT
I
SC
Parameter
Resolution
Integral Non-Linearity at FS, T
A
= 25°C
Full Scale Error
Differential Non-Linearity, T
A
= 25°C
Offset Error at V
OUT
Offset Error Tempco at V
OUT
Power Supply Rejection Ratio
Voltage Reference Range
Reference Input Leakage Current
Voltage Swing
Output Resistance @ V
OUT
Output Current (Source or Sink)
Output Short-Circuit Current
V
DD
= 5.5V
Test Conditions
Min
—
—
—
Typ
—
—
—
—
±0.3
10
80
—
—
—
5
2
30
20
Max
12
±16
±3
+4
±8
—
—
V
DD
– 1.2
±1.0
V
REF
—
—
50
50
Unit
Bits
LSB
%FS
LSB
mV
µv/°C
dB
V
µA
V
Ω
mA
mA
mA
All Codes (Note 2)
(Note 2)
V
DD
at DC
-1
—
—
—
0
—
V
REF
≤
(V
DD
– 1.2V)
R
OUT
(ohmic)
Source
Sink
0
—
—
—
—
NOTES:
1. SDA and SCL must be connected to V
DD
or GND.
2. Measured at V
OUT
≥
50mV refered to GND to avoid output buffer clipping.
TC1322-1
6/23/00
2
12-Bit Digital-to-Analog Converter with
Two-Wire Interface
TC1322
DYNAMIC PERFORMANCE:
(V
DD
= 2.7V to 5.5V, –40°C
≤
T
A
≤
85°C, unless otherwise noted.)
Symbol
SR
t
SETTLE
t
WU
Parameter
Voltage Output Slew Rate
Output Voltage Full Scale Settling Time
Wake-up Time
Digital Feedthrough and Crosstalk
Test Conditions
Min
—
—
—
Typ
0.8
10
20
Max
—
—
—
Unit
V/µs
µsec
µs
SDA = V
DD
, SCL = 100kHz
—
5
—
nV-s
SERIAL PORT INTERFACE:
(V
DD
= 2.7V to 5.5V, –40°C
≤
T
A
≤
85°C, unless otherwise noted.)
Symbol
V
IH
V
IL
V
OL
C
IN
I
LEAK
Parameter
Logic Input High
Logic Input Low
SDA Output Low
Input Capacitance SDA, SCL
I/O Leakage
Test Conditions
Min
2.4
—
Typ
—
—
—
—
5
—
Max
V
DD
0.6
0.4
0.6
—
±1
Unit
V
V
V
V
pF
µA
I
OL
= 3 mA (Sinking Current)
I
OL
= 6 mA
—
—
—
—
SERIAL PORT AC TIMING:
V
DD
= 2.7V to 5.5V, –40°C
≤
(T
A
= T
J
)
≤
85°C; C
L
= 80pF, unless otherwise noted.)
Symbol
f
SMB
t
IDLE
t
H(START)
t
SU(START)
t
SU(STOP)
t
H-DATA
t
SU-DATA
t
LOW
t
HIGH
t
F
t
R
t
POR
Parameter
SMBus Clock Frequency
Test Conditions
Min
10
4.7
4.0
4.7
4.0
100
100
Typ
—
—
—
—
—
—
—
—
—
—
—
500
Max
100
—
—
—
—
—
—
—
—
300
1000
—
Unit
kHz
µsec
µsec
µsec
µsec
nsec
nsec
µsec
µsec
nsec
nsec
µsec
Bus Free Time Prior to New Transition
Start Condition Hold Time
Start Condition Setup Time
Stop Condition Setup Time
Data In Hold Time
Data In Setup Time
Low Clock Period
High Clock Period
SMBus Fall Time
SMBus Rise Time
Power-On Reset Delay
10% to 10%
90% to 90%
90% to 10%
10% to 90%
V
DD
≥
V
POR
(Rising Edge)
90% SCL to 10% SDA
(for repeated Start Condition)
4.7
4
—
—
—
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
TC1322-1
6/23/00
Symbol
V
REF
SDA
SCL
GND
VOUT
NC
DAC_OUT
V
DD
Type
Input
Bi-Directional
Input
Input
Output
None
Output
Power
3
Description
Voltage Reference Input
SMBUS Serial Data
SMBUS Serial Clock
System Ground
Buffered DAC Output
Not Connected
Unbuffered DAC Output
Positive Power Supply Input
12-Bit Digital-to-Analog Converter with
Two-Wire Interface
TC1322
TIMING DIAGRAMS
SMBUS Write Timing Diagram
A
ILOW
B
IHIGH
C
D
E
F
G
H
I
J
K
L
M
SCL
SDA
tSU(START) tH(START)
tSU-DATA
tH-DATA
tSU(STOP)
tIDLE
A = Start Condition
B = MSB of Address Clocked into Slave
C = LSB of Address Clocked into Slave
D = R/W Bit Clocked into Slave
E = Slave Pulls SDA Line Low
F = Acknowledge Bit Clocked into Master
G = MSB of Data Clocked into Slave
H = LSB of Data Clocked into Slave
I = Slave Pulls SDA Line Low
J = Acknowledge Clocked into Master
K = Acknowledge Clock Pulse
L = Stop Condition, Data Executed by Slave
M = New Start Condition
SMBUS READ Timing Diagram
A
ILOW
B
IHIGH
C
D
E
F
G
H
I
J
K
SCL
SDA
tSU(START)
tH(START)
tSU-DATA
tSU(STOP)
tIDLE
A = Start Condition
B = MSB of Address Clocked into Slave
C = LSB of Address Clocked into Slave
D = R/W Bit Clocked into Slave
E = Slave Pulls SDA Line Low
F = Acknowledge Bit Clocked into Master
G = MSB of Data Clocked into Master
H = LSB of Data Clocked into Master
I = Acknowledge Clock Pulse
J = Stop Condition
K = New Start Condition
TC1322-1
6/23/00
4
12-Bit Digital-to-Analog Converter with
Two-Wire Interface
TC1322
PIN DESCRIPTION
V
REF
Input. Voltage Reference Input can range from 0V to
1.2V below V
DD
.
Reference Input
The reference pin, V
REF
, is a buffered high impedance
input and because of this the load regulation of the refer-
ence source need only to be able to tolerate leakage levels
of current (less than 1µA). V
REF
accepts a voltage range
from 0 to (V
DD
– 1.2V). Input capacitance is typically around
10 pF.
SDA
Bi-directional. Serial data is transferred on the SMBus
in both directions using this pin. See System Management
Bus Specification rev. 1.0 for timing diagrams.
SCL
Input. SMBus serial clock. Clocks data into and out of
the TC1322. See System Management Bus Specification
rev. 1.0 for timing diagrams.
Output Amplifier
The TC1322 DAC output is buffered with an internal
unity-gain rail-to-rail input/output amplifier with a typical slew
rate of 0.8V/µsec. Maximum full-scale transition settling
time is 10µsec to within
±1/2
LSB when loaded with 1kΩ in
parallel with 100pF.
GND
Input. Ground return for all TC1322 functions.
Standby Mode
The TC1322 allows the host to put it into a low power
(I
DD
= 0.5µA, typical) Standby mode. In this mode, the D/A
convertion is halted. The SMBus port operates normally.
Standby mode is enabled by setting the SHDN bit in the
CONFIG register. The table below summarizes this opera-
tion.
VOUT
Output. Buffered DAC output voltage. This voltage is a
function of the reference voltage and the contents of the
DATA register. See Functional Description section.
DAC_OUT
Output. Unbuffered DAC output voltage. This voltage is
a function of the reference voltage and the contents of the
DATA register. However, since it is unbuffered, care must be
taken that the pin is connected only to a high impedance
node.
Standby Mode Operation
SHDN Bit
0
1
Operating Mode
Normal
Standby
V
DD
Input. Positive power supply input. See electrical speci-
fications.
SMBus Slave Address
The TC1322 is internally programmed to have a default
SMBus address value of 1001 000b. Seven other addresses
are available by custom order (contact factory).
DETAILED DESCRIPTION
The TC1322 is a monolithic 12-bit digital-to-analog
converter that is designed to operate from a single supply
that can range from 2.7V to 5.5V. The DAC consists of a data
register (DATA), a configuration register (CONF), and a
current output amplifier. The TC1322 uses an external
reference which also determines the maximum output volt-
age.
The TC1322 uses a current-steering DAC based on an
array of matched current sources which goes into the
precision resistor that converts the contents of the Data
Register and V
REF
into an output voltage, V
OUT
given by:
V
OUT
= V
REF
(DATA/ 4096)
TC1322-1
6/23/00
SERIAL PORT OPERATION
The Serial Clock input (SCL) and bi-directional data port
(SDA) form a 2-wire bi-directional serial port for program-
ming and interrogating the TC1322. The following conven-
tions are used in this bus architecture:
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