TC3402
+1.8V, Low-Power, Quad-Input, 16-Bit Sigma-Delta A/D Converter
FEATURES
s
16-Bit Resolution at Eight Conversions Per
Second, Adjustable Down to 10-Bit Resolution at
512 Conversions Per Second
1.8V – 5.5V Operation, Low Power Operating .... 250
µ
A
............................................................ Sleep: 0.75
µ
A
Four True Differential Inputs with Built-In Multiplexer
MicroPort™ Serial Bus Requires Only Two
Interface Lines
Uses Internal or External Reference
Automatically Enters Sleep Mode When Not In Use
16-Pin QSOP and PDIP Packages
GENERAL DESCRIPTION
The TC3402 is a low cost, low power analog-to-digital
converter based on TelCom’s Sigma-Delta technology. It
will perform 16-bit conversions (15-bit plus sign) at up to
eight per second. The TC3402 is optimized for use as a
microcontroller peripheral in low cost, battery operated
systems. A voltage reference is included, or an external
reference can be used.
The TC3402’s 2-wire MicroPort™digital interface is
used for starting conversions and for reading out the data.
Driving the SCLK line low starts a conversion. After the
conversion starts, each additional falling edge (up to six)
detected on SCLK for t4 seconds reduces the A/D resolution
by one bit and cuts conversion time in half. After a conver-
sion is completed, clocking the SCLK line puts the MSB
through LSB of the resulting data word onto the SDAT line,
much like a shift register. The part automatically sleeps
when not performing a data conversion.
The TC3402 is available in 16-Pin PDIP and 16-Pin
QSOP packages.
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TYPICAL APPLICATIONS
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Consumer Electronics, Thermostats, CO
Monitors, Humidity Meters, Security Sensors
Embedded Systems, Data Loggers, Portable
Equipment
Medical Instruments
TYPICAL APPLICATION
V
BATT
ORDERING INFORMATION
Part No.
TC3402VPE
TC3402VQR
Package
16-Pin PDIP (Narrow)
16-Pin QSOP (Narrow)
Temp. Range
0°C to +85°C
0°C to +85°C
+
–
+
–
+
–
+
–
IN1+
IN1–
IN2+
IN2–
IN3+
IN3–
IN4+
IN4–
V
DD
SDAT
SCLK
ADDR 1
ADDR 2
I/01
I/02
I/03
I/04
V
CC
PIN CONFIGURATIONS
TC3402
µ
Controller
16-Pin PDIP/QSOP
IN1+
IN1–
IN2+
1
2
3
4
5
6
7
8
16
15
14
VDD
SCLK
A0
A1
IN4+
IN4–
SDAT
REF
OUT
REF
IN
REF
OUT
C1
0.1
µF
R3
390Ω
IN2–
IN3+
IN3–
REF
IN
GND
TC3402
13
12
11
10
9
TC3402-1
6/29/00
TelCom Semiconductor reserves the right to make changes in the circuitry and specifications of its devices.
+1.8V, Low-Power, Quad-Input,
16-Bit, Sigma-Delta, A/D Converter
TC3402
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage ...........................................................6.0V
Input Voltage ...................... (GND – 0.3V) to (V
DD
+ 0.3V)
Operating Temperature .................................. 0°C to 85°C
Maximum Chip Temperature ................................. +150°C
Storage Temperature Range ................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
DC ELECTRICAL CHARACTERISTICS:
T
A
= 25°C and V
DD
= 2.7V, unless otherwise specified. Specifications
in Bold type apply over a temperature range of 0°C to 85°C. V
REF
= 1.25V, Internal Clock Freq = 520kHz
Symbol
V
DD
I
DD
I
DD(SLEEP)
I
DD(SLEEP)
RES
INL
V
OS
V
NOISE
CMR
FSE
PSRR
Parameter
Test Conditions
Min
1.8
—
—
—
—
Typ
—
250
0.75
1.8
16
.0038
—
60
75
0.4%
75
—
—
1
2
2.0
—
1
1.193
10
—
—
—
1
Max
5.5
—
1.5
3.0
—
—
Unit
V
µA
µA
µA
Bits
%FSR
%FSR
µVrms
dB
%FS
dB
V
V
nA
pF
MΩ
V
µA
V
µA
µA
V
V
µA
POWER SUPPLY
Supply Voltage
Supply Current, During Data Conversion
Supply Current, Sleep Mode
T
A
= +25°C
ACCURACY
(Differential Inputs)
Resolution
Integral Non-Linearity
Offset Error
Refered to input
Common Mode Rejection
Full Scale Error
Power Supply Rejection Ratio
Differential Input Voltage
Absolute Voltage Range
on INn
+
, INn
–,
INn
Input Bias Current
C
IN
R
IN
Input Sampling Capacitance
Differential Input Resistance
REF
IN
Voltage Range
REF
IN
Input Current
REF
OUT
Voltage
REF
OUT
Current Sink Capability
REF
OUT
Current Source Capability
Input Low Voltage
Input High Voltage
Leakage Current
1. Differential input voltage defined as (V
IN
+ – V
IN
–)
2. Resistance from INn+ to INn– or INn to GND.
V
DD
= 2.7V
IN = IN = 0V
at DC
V
DD
= 2.5V to 3.5V
(Note 1)
+
–
—
—
—
—
—
—
—
GND
—
—
±
1.0
—
—
—
—
2.5
V
DD
100
—
—
1.25
—
—
—
—
0.3 x V
DD
—
—
INn
+
, INn
V
IN
±
(Note 2)
—
0
—
—
—
300
—
0.7 x V
DD
—
REF
IN
, REF
OUT
V
REF
I
REF
V
REFOUT
REF
SINK
REF
SRC
SCLK, ADDR
V
IL
V
IH
I
LEAK
Notes:
TC3402-1 6/29/00
2
+1.8V, Low-Power, Quad-Input,
16-Bit, Sigma-Delta, A/D Converter
TC3402
DC ELECTRICAL CHARACTERISTICS (CONT.):
T
A
= 25°C and V
DD
= 2.7V, unless otherwise specified.
Specifications in Bold type apply over a temperature range of 0°C to 85°C.
Symbol
SDAT
V
OL
V
OH
Output Low Voltage
Output High Voltage (SDAT)
I
OL
= 1.5mA
I
SOURCE
= 400µa (Note 2)
—
0.9 x V
DD
—
—
0.4
—
V
V
Parameter
Test Conditions
Min
Typ
Max
Unit
AC ELECTRICAL CHARACTERISTICS:
T
A
= 25°C and V
DD
= 2.7V, unless otherwise specified. Specifications
in Bold type apply over a temperature range of 0°C to 85°C. V
REF
= 1.25V, Internal Clock Freq = 520kHz
Symbol
t
1
t
2
t
3
Parameter
Resolution Reduction Clock Width
Conversion Time (15-Bit Plus Sign)
Conversion Time (14-Bit Plus Sign)
Conversion Time (13-Bit Plus Sign)
Conversion Time (12-Bit Plus Sign)
Conversion Time (11-Bit Plus Sign)
Conversion Time (10-Bit Plus Sign)
Conversion Time (9-Bit Plus Sign)
t
4
t
5
t
6
t
7
t
8
Resolution Reduction Window
SCLK to Data Valid
Address Setup
Address Hold
Acknowledge Delay
Description
Width of SCLK (Negative)
Width of SCLK (Positive)
16-bit conversion, T
A
= 25° (Note 1)
15-bit conversion
14-bit conversion
13-bit conversion
12-bit conversion
11-bit conversion
10-Bit conversion
Width of SCLK
SCLK falling edge to SDAT valid
Address valid to SCLK
SCLK to address valid hold
SCLK to SDAT delay
Min
1
1
—
—
—
—
—
—
—
—
1000
0
1000
—
Typ
—
—
125
t3/2.0
t3/4.0
t3/7.8
t3/15.1
t3/28.6
t3/51.4
t3/85.7
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
1000
Unit
µsec
µsec
msec
msec
msec
msec
msec
msec
msec
msec
nsec
nsec
nsec
nsec
Notes: 1. Nominal temperature drift is -2830 ppm/°C for temperature less than 25°C and -1340 ppm/°C for
temperatures greater than 25°C.
2. @V
DD
=1.8V, I
SOURCE
200µa
TC3402-1 6/29/00
3
+1.8V, Low-Power, Quad-Input,
16-Bit, Sigma-Delta, A/D Converter
TC3402
PIN DESCRIPTION
TC3402
Pin No.
1,3,5,12
Name
INn
+
Description
Analog Input. This is the positive terminal of a true differential input
consisting of INn
+
and INn
–
. V
IN(n)
= (INn
+
– INn
–
).(See
Electrical
Characteristics
.)
Analog Input. This is the negative terminal of a true differential input
consisting of INn
+
and INn
–
. V
IN(n)
= (INn
+
– INn
–
) INn
–
can swing to,
but not below, ground. (See
Electrical Characteristics
.)
Analog Input. The converter’s reference voltage is the differential
between this pin and ground times two. It may be connected to
REF
OUT
as shown on page 1 or scaled using a resistor divider. Any user
supplied reference voltage or the power supply rail may be used in place of REF
OUT
.
Ground Terminal.
Analog Output. The internal reference connects to this pin. It may be
scaled externally, if desired, and tied to the REF
IN
input to provide the
converter’s reference voltage. Care must be taken in connecting
external circuitry to this pin. (See
Electrical Characteristics
.)
Digital Output (push-pull). This is the MicroPort™ serial data output.
SDAT is driven low while the TC3402 is converting data, effectively
providing a “busy” signal. After the conversion is complete, every high-
to-low transition on the SCLK pin puts a bit from the resulting data word
on the SDAT pin (from MSB to LSB).
Digital Input. Controls analog multiplexer in conjunction with A0 to select
one of the four Input channels. This address is latched at the falling edge
of the SCLK, which starts an A/D conversion. A1,A0 = 00 = Input 1;
01 = Input 2; 10 = Input 3; 11 = Input 4.
Digital Input. Controls analog multiplexer in conjunction with A1 to select
one of four Input channels. This address is latched at the falling edge of
the SCLK, which starts an A/D conversion. A1,A0 = 00 = Input 1;
01 = Input 2; 10 = Input 3; 11 = Input 4.
Digital Input. This is the MicroPort™ serial clock input. After the conversion starts, each
additional falling edge (up to six) detected on SCLK for t4 seconds reduces the A/D
resolution by one bit. When the conversion is complete, the data word can be shifted out on
the SDAT pin by clocking the SCLK pin.
Power Supply Input. (See Electrical Characteristics.)
2,4,6,11
INn
–
7
REF
IN
8
9
GND
REF
OUT
10
SDAT
13
A1
14
A0
15
SCLK
16
V
DD
TC3402-1 6/29/00
4
+1.8V, Low-Power, Quad-Input,
16-Bit, Sigma-Delta, A/D Converter
TC3402
GENERAL THEORY OF OPERATION
The TC3402 is a 16-bit sigma-delta A/D converter. It
has four differential inputs and an analog multiplexer. The
detailed description of the key components of the TC3402 is
outlined below. (Also refer to the
A/D Operational Flowchart
on page 9 and the Timing Diagrams in Figures 2 through 4).
Table 1. Data Conversion Word vs. Voltage Input
(REF
IN
= 1.193V)
Data Word
INn
+
– INn
–
(Volts)
0111 1111 1111 1111
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
2.38596 (Positive Full Scale)
72.8 E – 6
0
–72.8 E – 6
–2.38596 (Negative Full Scale)
Reserved Code
A/D Converter Operation
When the TC3402 is not converting, it is in sleep mode
with both the SCLK and SDAT lines high. An A/D conversion
is initiated by a high to low transition on the SCLK line at
which time the internal clock of the TC3402 is started and
the address value (A0 and A1) is internally latched. The
address value steers the analog multiplexer to select the
input channel to be converted. Each additional high to low
transition of SCLK (following the initial SCLK falling edge)
and during the time interval t4 will decrement the conversion
accuracy by one bit and reduce the conversion time by one
half. The time interval t4 is referred to as the resolution
reduction window. The minimum conversion resolution is 10
bits so any more than 6 SCLK transitions during t4 will be
ignored.
After each high to low transition of SCLK, in the t4
interval, the SDAT output is driven high by the TC3402 to
acknowledge that the conversion has been decremented.
When the SCLK returns high or the t4 interval ends, the
SDAT line returns low (see Figure 2). When the conversion
is complete SDAT is driven high. The 3402 now enters sleep
mode and the conversion value can be read as a serial data
word on the SDAT line.
The SCLK input has a filter which rejects any positive or
negative pulse of width less than 50nsec to reduce noise.
The rejection width of this pulse can vary between 50nsec
and 750nsec depending on processing parameters and
supply voltage.
Figure 3 shows a truth table for determining the mode of
operation for the TC3402 part by recording the value of
SDAT for SCLK in a high, then low, then high state. For
example, if SCLK goes through a 1-0-1 transition and the
corresponding values of SDAT are 1-1-0, then the SCLK
falling edge started a new data conversion. A 0-1-0 for SDAT
would have indicated a resolution reduction had occurred.
This is useful if the microcontroller has a watchdog reset or
otherwise loses track of where the TC3402 part is in the
conversion and data readout sequence. The microcontroller
can simply transition SCLK until it “finds” a Start Conversion
condition.
Reading the Data Word
After the conversion is complete and SDAT goes high,
the conversion value can be clocked serially onto the SDAT
line by high to low transitions of the SCLK. The data word is
in two’s compliment format with the sign bit clocked onto the
SDAT line first followed by the MSB and ending in the LSB.
For a 16 bit conversion the data word would consist of a sign
bit follwed by 15 magnitude bits, Table 1 shows the data
word versus input voltage for a 16 bit conversion. Note that
the full scale input voltage range is
±(2
REF
IN
– 1LSB). When
REF
OUT
is fed back directly to REF
IN
, an LSB is 73µV for a
16 bit convertion, as REF
OUT
is typically 1.193V.
Figure 3 shows typical SCLK and SDAT waveforms for
16, 12 and 10 bit conversions. Note that any complete
convert and read cycle requires 17 negative edge clock
pulses. The first is the convert command. Then, up to six of
these can occur in the resolution reduction window, t4, to
decrement accuracy. The remaining pulses clock out the
conversion data word.
5
TC3402-1 6/29/00
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