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TC4467MJDG

1.2 A 4 CHANNEL, NAND GATE BASED MOSFET DRIVER, CDIP14, 0.300 INCH, CERDIP-14

器件类别:模拟混合信号IC    驱动程序和接口   

厂商名称:Microchip(微芯科技)

厂商官网:https://www.microchip.com

器件标准:

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Microchip(微芯科技)
零件包装代码
DIP
包装说明
0.300 INCH, CERDIP-14
针数
14
Reach Compliance Code
compliant
ECCN代码
EAR99
高边驱动器
YES
接口集成电路类型
NAND GATE BASED MOSFET DRIVER
JESD-30 代码
R-GDIP-T14
JESD-609代码
e3
长度
19.305 mm
功能数量
4
端子数量
14
最高工作温度
125 °C
最低工作温度
-55 °C
标称输出峰值电流
1.2 A
封装主体材料
CERAMIC, GLASS-SEALED
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
5.08 mm
最大供电电压
18 V
最小供电电压
4.5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
MATTE TIN
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
断开时间
0.1 µs
接通时间
0.1 µs
宽度
7.62 mm
文档预览
TC4467/TC4468/TC4469
Logic-Input CMOS Quad Drivers
Features
• High Peak Output Current: 1.2 A
• Wide Operating Range:
- 4.5 V to 18 V
• Symmetrical Rise/Fall Times: 25 nsec
• Short, Equal Delay Times: 75 nsec
• Latch-proof. Will Withstand 500 mA Inductive
Kickback
• 3 Input Logic Choices:
- AND / NAND / AND + Inv
• ESD Protection on All Pins: 2 kV
General Description
The TC4467/TC4468/TC4469 devices are a family of
four-output CMOS buffers/MOSFET drivers with 1.2 A
peak drive capability. Unlike other MOSFET drivers,
these devices have two inputs for each output. The
inputs are configured as logic gates: NAND (TC4467),
AND (TC4468) and AND/INV (TC4469).
The TC4467/TC4468/TC4469 drivers can continuously
source up to 250 mA into ground referenced loads.
These devices are ideal for direct driving low current
motors or driving MOSFETs in a H-bridge configuration
for higher current motor drive (see Section 5.0 for
details). Having the logic gates onboard the driver can
help to reduce component count in many designs.
The TC4467/TC4468/TC4469 devices are very robust
and highly latch-up resistant. They can tolerate up to
5 V of noise spiking on the ground line and can handle
up to 0.5 A of reverse current on the driver outputs.
The TC4467/4468/4469 devices are available in
commercial, industrial and military temperature ranges.
Applications
General Purpose CMOS Logic Buffer
Driving All Four MOSFETs in an H-Bridge
Direct Small Motor Driver
Relay or Peripheral Drivers
CCD Driver
Pin-Switching Network Driver
Package Types
14-Pin PDIP/CERDIP
1A 1
1B 2
2A 3
2B 4
3A 5
3B 6
GND 7
TC4467
TC4468
TC4469
14 V
DD
13 1Y
12 2Y
11 3Y
10 4Y
9 4B
8 4A
16-Pin SOIC (Wide)
1A
1B
2A
2B
3A
3B
GND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
DD
1Y
2Y
3Y
4Y
4B
4A
TC4467
TC4468
TC4469
2001-2012 Microchip Technology Inc.
DS21425C-page 1
TC4467/TC4468/TC4469
Logic Diagrams
TC4467
V
DD
14
1A
1B
2A
2B
3A
3B
4A
4B
1
2
3
4
5
6
8
9
TC4468
V
DD
14
13 1Y
12 2Y
11 3Y
10 4Y
1A 1
1B 2
2A 3
2B 4
3A 5
3B 6
4A 8
4B 9
7
GND
13 1Y
12 2Y
11 3Y
10 4Y
1A 1
1B 2
2A 3
2B 4
3A 5
3B 6
4A 8
4B 9
TC4469
V
DD
14
13 1Y
12 2Y
11 3Y
10 4Y
7
GND
TC446X
V
DD
Output
7
GND
DS21425C-page 2
2001-2012 Microchip Technology Inc.
TC4467/TC4468/TC4469
1.0
ELECTRICAL
CHARACTERISTICS
†Notice:
Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings†
Supply Voltage ...............................................................+20 V
Input Voltage ............................. (GND – 5 V) to (V
DD
+ 0.3 V)
Package Power Dissipation: (T
A
70°C)
PDIP...................................................................800 mW
CERDIP .............................................................840 mW
SOIC ..................................................................760 mW
Package Thermal Resistance:
CERDIP R
J-A
...................................................100°C/W
CERDIP R
J-C
.....................................................23°C/W
PDIP R
J-A
..........................................................80°C/W
PDIP R
J-C
..........................................................35°C/W
SOIC R
J-A
..........................................................95°C/W
SOIC R
J-C
..........................................................28°C/W
Operating Temperature Range:
C Version ................................................... 0°C to +70°C
E Version.................................................-40°C to +85°C
M Version ..............................................-55°C to +125°C
Maximum Chip Temperature ....................................... +150°C
Storage Temperature Range .........................-65°C to +150°C
ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise noted, T
A
= +25°C, with 4.5 V
V
DD
18
V.
Parameters
Input
Logic 1, High Input Voltage
Logic 0, Low Input Voltage
Input Current
Output
High Output Voltage
Low Output Voltage
Output Resistance
Peak Output Current
Continuous Output Current
Latch-Up Protection Withstand
Reverse Current
Switching Time (Note 1)
Rise Time
Fall Time
Delay Time
Delay Time
Power Supply
Power Supply Current
Power Supply Voltage
Note
1:
Sym
Min
Typ
Max
Units
Conditions
V
IH
V
IL
I
IN
V
OH
V
OL
R
O
I
PK
I
DC
I
2.4
-1.0
V
DD
– 0.025
10
1.2
500
V
DD
0.8
+1.0
0.15
15
300
500
V
V
µA
V
V
A
mA
mA
Note 3
Note 3
0 VV
IN
V
DD
I
LOAD
= 100 µA
(Note 1)
I
LOAD
= 10 mA
(Note 1)
I
OUT
= 10 mA, V
DD
= 18 V
Single Output
Total Package
4.5 VV
DD
16
V
t
R
t
F
t
D1
t
D2
I
S
V
DD
4.5
15
15
40
40
1.5
25
25
75
75
4
18
nsec
nsec
nsec
nsec
mA
V
Figure 4-1
Figure 4-1
Figure 4-1
Figure 4-1
Note 2
2:
3:
Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching
times are ensured by design.
When driving all four outputs simultaneously in the same direction, V
DD
will be limited to 16 V. This reduces the chance that internal dv/dt
will cause high-power dissipation in the device.
The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 µsec
to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below
the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
2001-2012 Microchip Technology Inc.
DS21425C-page 3
TC4467/TC4468/TC4469
ELECTRICAL SPECIFICATIONS (OPERATING TEMPERATURES)
Electrical Characteristics:
Unless otherwise noted, over operating temperature range with 4.5 V
V
DD
18
V.
Parameters
Input
Logic 1, High Input Voltage
Logic 0, Low Input Voltage
Input Current
Output
High Output Voltage
Low Output Voltage
Output Resistance
Peak Output Current
Continuous Output Current
Latch-Up Protection Withstand
Reverse Current
Switching Time (Note 1)
Rise Time
Fall Time
Delay Time
Delay Time
Power Supply
Power Supply Current
Power Supply Voltage
Note
1:
Sym
Min
Typ
Max
Units
Conditions
V
IH
V
IL
I
IN
V
OH
V
OL
R
O
I
PK
I
DC
I
2.4
-10
V
DD
– 0.025
20
1.2
500
0.8
10
0.30
30
300
500
V
V
µA
V
V
A
mA
mA
Note 3
Note 3
0 VV
IN
V
DD
I
LOAD
= 100 µA
(Note 1)
I
LOAD
= 10 mA
(Note 1)
I
OUT
= 10 mA, V
DD
= 18 V
Single Output
Total Package
4.5 VV
DD
16
V
t
R
t
F
t
D1
t
D2
I
S
V
DD
4.5
15
15
40
40
50
50
100
100
8
18
nsec
nsec
nsec
nsec
mA
V
Figure 4-1
Figure 4-1
Figure 4-1
Figure 4-1
Note 2
2:
3:
Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching
times are ensured by design.
When driving all four outputs simultaneously in the same direction, V
DD
will be limited to 16 V. This reduces the chance that internal dv/dt
will cause high-power dissipation in the device.
The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 µsec
to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below
the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
TRUTH TABLE
Part No.
Inputs A
Inputs B
Outputs TC446X
Legend: H = High
H
H
L
L = Low
TC4467 NAND
H
L
H
L
H
H
L
L
H
H
H
H
TC4468 AND
H
L
L
L
H
L
L
L
L
H
H
L
TC4469 AND/INV
H
L
H
L
H
L
L
L
L
DS21425C-page 4
2001-2012 Microchip Technology Inc.
TC4467/TC4468/TC4469
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
T
A
= +25°C, with 4.5 V
V
DD
18
V.
140
Note:
140
2200 pF
0p
120
100
t
RISE
(nsec)
120
2200 pF
100
1500 pF
1600 p
pF
1000 pF
80
60
40
20
0
3
t
FALL
(nsec)
80
60
40
20
1000 pF
470 pF
470 pF
100 pF
100 p
pF
5
7
9
13
V
SUPPLY
(V)
11
15
17
19
0
3
5
7
9
11
13
V
SUPPLY
(V)
15
17
19
FIGURE 2-1:
Voltage.
Rise Time vs. Supply
FIGURE 2-4:
Voltage.
140
Fall Time vs. Supply
140
120
100
t
RISE
(nsec)
5V
120
100
5V
t
FALL
(nsec)
80
60
40
20
0
100
1000
C
LOAD
(pF)
10,000
80
60
40
20
0
100
1000
C
LOAD
(pF)
10 V
15 V
10 V
15 V
10,000
FIGURE 2-2:
Load.
25
20
V
SUPPLY
= 17.5 V
C
LOAD
= 470 pF
Rise Time vs. Capacitive
FIGURE 2-5:
Load.
80
Fall Time vs. Capacitive
C
LOAD
= 470 pF
4
t
FALL
t
RISE
DELAY TIME (nsec)
60
t
D1
TIME (nsec)
15
10
5
0
-50
40
t
D2
20
0
-25
0
25
50
75
100
125
4
6
8
10
12
14
16
18
TEMPERATURE (
°
C)
V
SUPPLY
(V)
FIGURE 2-3:
Temperature.
Rise/Fall Times vs.
FIGURE 2-6:
Supply Voltage.
Propagation Delay Time vs.
2001-2012 Microchip Technology Inc.
DS21425C-page 5
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