TC4467
TC4468
TC4469
LOGIC-INPUT CMOS QUAD DRIVERS
FEATURES
s
s
s
s
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High Peak Output Current ............................... 1.2A
Wide Operating Range ............................ 4.5 to 18V
Symmetrical Rise and Fall Times ................ 25nsec
Short, Equal Delay Times ............................ 75nsec
Latchproof! Withstands 500mA Inductive Kickback
3 Input Logic Choices
— AND / NAND / AND + Inv
2kV ESD Protection on All Pins
1
2
3
4
5
6
7
GENERAL DESCRIPTION
The TC446X family of four-output CMOS buffer/drivers
are an expansion from our earlier single- and dual-output
drivers. Each driver has been equipped with a two-input
logic gate for added flexibility.
The TC446X drivers can source up to 250 mA into loads
referenced to ground. Heavily loaded clock lines, coaxial
cables, and piezoelectric transducers can all be easily
driven with the 446X series drivers. The only limitation on
loading is that total power dissipation in the IC must be kept
within the power dissipation limits of the package.
The TC446X series will not latch under any conditions
within their power and voltage ratings. They are not subject
to damage when up to 5V of noise spiking (either polarity)
occurs on the ground line. They can accept up to half an amp
of inductive kickback current (either polarity) into their out-
puts without damage or logic upset. In addition, all terminals
are protected against ESD to at least 2000V.
APPLICATIONS
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s
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General-Purpose CMOS Logic Buffer
Driving All Four MOSFETs in an H-Bridge
Direct Small Motor Driver
Relay or Peripheral Drivers
CCD Driver
Pin-Switching Network Driver
ORDERING INFORMATION
Part No.
TC446xCOE
TC446xCPD
TC446xEJD
TC446xMJD
Package
16-Pin SOIC (Wide)
14-Pin Plastic DIP
14-Pin CerDIP
14-Pin CerDIP
Temp. Range
0° to +70°C
0° to +70°C
– 40° to +85°C
– 55° to +125°C
LOGIC DIAGRAMS
x indicates a digit must be added in this position to define the device
input configuration: TC446x — 7
NAND
8
AND
9
AND with INV
TC4467
1A
1B
2A
2B
3A
3B
4A
4B
1
2
3
4
5
6
8
9
VDD
14
13
1Y
TC4468
1A
1B
2A
2B
3A
3B
4A
4B
1
2
3
4
5
6
8
9
VDD
14
13
1Y
TC4469
1A
1B
2A
2B
3A
3B
4A
4B
1
2
3
4
5
6
8
9
VDD
14
13
1Y
TC446X
VDD
12
2Y
12
2Y
12
2Y
OUTPUT
11
3Y
11
3Y
11
3Y
10
4Y
10
4Y
10
4Y
7
GND
7
GND
7
GND
TC4467/8/9-6 10/21/96
8
4-261
TELCOM SEMICONDUCTOR, INC.
LOGIC-INPUT CMOS
QUAD DRIVERS
TC4467
TC4468
TC4469
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage ......................................................... +20V
Input Voltage ......................... (GND – 5V) to (V
DD
+ 0.3V)
Maximum Chip Temperature
Operating ........................................................ +150°C
Storage ............................................. – 65° to +150°C
Maximum Lead Temperature
(Soldering, 10 sec) ......................................... +300°C
Operating Ambient Temperature Range
C Device .................................................. 0° to +70°C
E Device ............................................. – 40° to +85°C
M Device ........................................... – 55° to +125°C
Package Power Dissipation (T
A
≤
70°C)
14-Pin CerDIP ................................................840mW
14-Pin Plastic DIP ...........................................800mW
16-Pin Wide SOIC ..........................................760mW
Package Thermal Resistance
14-Pin CerDIP
R
θJ-A
......................................
100°C/W
R
θJ-C
.........................................
23°C/W
14-Pin Plastic DIP R
θJ-A
.........................................
80°C/W
R
θJ-C
.........................................
35°C/W
16-Pin Wide SOIC R
θJ-A
.........................................
95°C/W
R
θJ-C
.........................................
28°C/W
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS:
Measured at T
A
= +25°C with 4.5V
≤
V
DD
≤
18V, unless otherwise specified.
Symbol
Input
V
IH
V
IL
I
IN
Logic 1, High Input Voltage
Logic 0, Low Input Voltage
Input Current
High Output Voltage
Low Output Voltage
Output Resistance
Peak Output Current
Continuous Output Current
Latch-Up Protection
Withstand Reverse Current
Rise Time
Fall Time
Delay Time
Delay Time
Power Supply Current
Power Supply Voltage
Note 3
Note 3
0V
≤
V
IN
≤
V
DD
I
LOAD
= 100µA (Note 1)
I
LOAD
= 10mA (Note 1)
I
OUT
= 10mA, V
DD
= 18V
Single Output
Total Package
4.5V
≤
V
DD
≤
16V
2.4
0
–1
V
DD
– 0.025
—
—
—
—
500
—
—
—
—
—
10
1.2
—
—
V
DD
0.8
1
—
0.15
15
—
300
500
—
V
V
µA
V
V
Ω
A
mA
mA
Parameter
Test Conditions
Min
Typ
Max
Unit
Output
V
OH
V
OL
R
O
I
PK
I
DC
I
Switching Time
t
R
t
F
t
D1
t
D2
I
S
V
DD
Figure 1
Figure 1
Figure 1
Figure 1
—
—
—
—
—
4.5
15
15
40
40
1.5
—
25
25
75
75
4
18
nsec
nsec
nsec
nsec
mA
V
Power Supply
Note 2
TRUTH TABLE
Part No.
INPUTS A
INPUTS B
OUTPUTS TC446X
H = High
4-262
L = Low
TC4467 NAND
H
H
L
H
L
H
L
H
H
L
L
H
H
H
H
TC4468 AND
H
L
L
L
H
L
L
L
L
TC4469 AND/INV
H
H
L
H
L
H
L
H
L
L
L
L
TELCOM SEMICONDUCTOR, INC.
LOGIC-INPUT CMOS
QUAD DRIVERS
TC4467
TC4468
TC4469
ELECTRICAL CHARACTERISTICS:
Measured throughout operating temperature range with 4.5V
≤
V
DD
≤
18V,
unless otherwise specified.
Symbol
Input
V
IH
V
IL
I
IN
Logic 1, High Input Voltage
Logic 0, Low Input Voltage
Input Current
High Output Voltage
Low Output Voltage
Output Resistance
Peak Output Current
Latch-Up Protection
Withstand Reverse Current
Rise Time
Fall Time
Delay Time
Delay Time
Power Supply Current
Power Supply Voltage
(Note 3)
(Note 3)
0V
≤
V
IN
≤
V
DD
I
LOAD
= 100
µA
(Note 1)
I
LOAD
= 10 mA (Note 1)
I
OUT
= 10 mA, V
DD
= 18V
4.5V
≤
V
DD
≤
16V
2.4
—
– 10
V
DD
– 0.025
—
—
—
500
—
—
—
—
—
20
1.2
—
—
0.8
10
—
0.30
30
—
—
V
V
µA
V
V
Ω
A
mA
1
Parameter
Test Conditions
Min
Typ
Max
Unit
2
3
4
5
6
7
Output
V
OH
V
OL
R
O
I
PK
I
Switching Time
t
R
t
F
t
D1
t
D2
I
S
I
S
Figure 1
Figure 1
Figure 1
Figure 1
—
—
—
—
—
4.5
—
—
—
—
—
—
50
50
100
100
8
18
nsec
nsec
nsec
nsec
mA
V
Power Supply
Note 2
NOTES:
1. Totem-pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device.
2. When driving all four outputs simultaneously in the same direction, V
DD
shall be limited to 16V. This reduces the chance that internal
dv/dt will cause high-power dissipation in the device.
3. The input threshold has about 50 mV of hysteresis centered at approximately 1.5V. Slow moving inputs will force the device to
dissipate high peak currents as the input transitions through this band. Input rise times should be kept below 5
µs
to avoid high internal
peak currents during input transitions. Static input levels should also be maintained above the maximum or below the minimum input
levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
PIN CONFIGURATIONS
16-Pin SOIC (Wide)
1A
1B
2A
2B
3A
3B
GND
GND
1
2
3
4
5
6
7
8
16
15
14
13
V
DD
V
DD
1Y
2Y
3Y
4Y
4B
4A
14-Pin Plastic DIP/CerDIP
1A 1
1B 2
2A 3
2B 4
3A 5
3B 6
GND 7
14 V
DD
13 1Y
12 2Y
TC4467/8/9
12
11
10
9
TC4467/8/9
11 3Y
10 4Y
9
8
4B
4A
8
4-263
TELCOM SEMICONDUCTOR, INC.
LOGIC-INPUT CMOS
QUAD DRIVERS
TC4467
TC4468
TC4469
Supply Bypassing
Large currents are required to charge and discharge
large capacitive loads quickly. For example, charging a
1000 pF load to 18V in 25nsec requires 0.72A from the
device's power supply.
To guarantee low supply impedance over a wide fre-
quency range, a 1
µF
film capacitor in parallel with one or two
low-inductance 0.1
µF
ceramic disk capacitors with short
lead lengths (<0.5 in.) normally provide adequate bypass-
ing.
Three components make up total package power
dissipation:
(1) Load-caused dissipation (P
L
)
(2) Quiescent power (P
Q
)
(3) Transition power (P
T
).
A capacitive-load-caused dissipation (driving MOSFET
gates), is a direct function of frequency, capacitive load, and
supply voltage. The power dissipation is:
P
L
= f C V
S2
,
where: f = Switching frequency
C = Capacitive load
V
S
= Supply voltage.
A resistive-load-caused dissipation for ground-refer-
enced loads is a function of duty cycle, load current, and
load voltage. The power dissipation is:
P
L
= D (V
S
– V
L
) I
L
,
where: D = Duty cycle
V
S
= Supply voltage
V
L
= Load voltage
I
L
= Load current.
A resistive-load-caused dissipation for supply-refer-
enced loads is a function of duty cycle, load current, and
output voltage. The power dissipation is:
P
L
= D V
O
I
L
,
where: f = Switching frequency
V
O
= Device output voltage
I
L
= Load current.
Quiescent power dissipation depends on input signal
duty cycle. Logic HIGH outputs result in a lower power
dissipation mode, with only 0.6 mA total current drain (all
devices driven). Logic LOW outputs raise the current to 4 mA
maximum. The quiescent power dissipation is:
P
Q
= V
S
(D (IH) + (1–D)I
L
),
where: I
H
= Quiescent current with all outputs LOW
(4 mA max)
I
L
= Quiescent current with all outputs HIGH
(0.6 mA max)
D = Duty cycle
V
S
=Supply voltage.
TELCOM SEMICONDUCTOR, INC.
Grounding
The TC4467 and TC4469 contain inverting drivers.
Potential drops developed in common ground impedances
from input to output will appear as negative feedback and
degrade switching speed characteristics. Instead, individual
ground returns for input and output circuits, or a ground
plane, should be used.
Input Stage
The input voltage level changes the no-load or quies-
cent supply current. The N-channel MOSFET input stage
transistor drives a 2.5 mA current source load. With logic "0"
outputs, maximum quiescent supply current is 4 mA. Logic
"1" output level signals reduce quiescent current to 1.4 mA
maximum. Unused driver inputs must be connected to V
DD
or V
SS
. Minimum power dissipation occurs for logic "1"
outputs.
The drivers are designed with 50 mV of hysteresis. This
provides clean transitions and minimizes output stage cur-
rent spiking when changing states. Input voltage thresholds
are approximately 1.5V, making any voltage greater than
1.5V up to V
DD
a logic 1 input . Input current is less than 1
µA
over this range.
Power Dissipation
The supply current versus frequency and supply current
versus capacitive load characteristic curves will aid in deter-
mining power dissipation calculations. TelCom Semicon-
ductor's CMOS drivers have greatly reduced quiescent DC
power consumption.
Input signal duty cycle, power supply voltage and load
type, influence package power dissipation. Given power
dissipation and package thermal resistance, the maximum
ambient operating temperature is easily calculated. The 14-
pin plastic package junction-to-ambient thermal resistance
is 83.3°C/W. At +70°C, the package is rated at 800mW
maximum dissipation. Maximum allowable chip tempera-
ture is +150°C.
4-264
LOGIC-INPUT CMOS
QUAD DRIVERS
TC4467
TC4468
TC4469
Transition power dissipation arises in the
complementary configuration (TC446X) because the
output stage N-channel and P-channel MOS transistors
are ON simultaneously for a very short period when the
output changes. The transition power dissipation is
approximately:
P
T
= f V
S
(10
10
–9
).
Maximum operating temperature:
T
J
–
θ
JA
(P
D
) = 141°C,
where: T
J
= Maximum allowable junction temperature
(+150°C)
θ
JA
= Junction-to-ambient thermal resistance
(83.3°C/W) 14-pin plastic package.
NOTE:
Ambient operating temperature should not exceed +85°C for
"EJD" device or +125°C for "MJD" device.
1
2
3
4
Package power dissipation is the sum of load, quies-
cent and transition power dissipations. An example shows
the relative magnitude for each term:
C = 1000 pF capacitive load
V
S
= 15V
D = 50%
f = 200 kHz
P
D
= Package Power Dissipation = P
L
+ P
Q
+ P
T
= 45 mW + 35 mW + 30 mW = 110 mW.
VDD
1 µF FILM
14
1
2
3
4
5
6
8
9
7
0.1 µF CERAMIC
+5V
13
90%
1A
1B
2A
2B
3A
3B
4A
4B
VOUT
470 pF
INPUT
(A, B)
0V
VDD
5
90%
tF
12
10%
90%
t
R
10%
tD2
11
OUTPUT
10
0V
tD1
10%
Input: 100 kHz, square wave,
t
RISE
= t
FALL
≤
10nsec
Figure 1. Switching Time Test Circuit
6
7
8
TELCOM SEMICONDUCTOR, INC.
4-265
