TC58FVT321/B321FT/XB-70,-10
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
32-MBIT (4M
×
8 BITS / 2M
×
16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVT321/B321 is a 33,554,432-bit, 3.0-V read-only electrically erasable and programmable flash memory
organized as 4,194,304 words
×
8 bits or as 2,097,152 words
×
16 bits. The TC58FVT321/B321 features commands
for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands are based on
the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The
TC58FVT321/B321 also features a Simultaneous Read/Write operation so that data can be read during a Write or
Erase operation.
FEATURES
•
•
•
•
Power supply voltage
V
DD
=
2.7 V~3.6 V
Operating temperature
Ta
= −40°C~85°C
Organization
4M
×
8 bits / 2M
×
16 bits
Functions
Simultaneous Read/Write
Auto Program, Auto Erase
Fast Program Mode / Acceleration Mode
Program Suspend/Resume
Erase Suspend/Resume
data polling / Toggle bit
block protection, boot block protection
Automatic Sleep, support for hidden ROM area
common flash memory interface (CFI)
Byte/Word Modes
•
•
•
•
•
•
Block erase architecture
8
×
8 Kbytes / 63
×
64 Kbytes
Boot block architecture
TC58FVT321FT/XB: top boot block
TC58FVB321FT/XB: bottom boot block
Mode control
Compatible with JEDEC standard commands
Erase/Program cycles
10
5
cycles typ.
Access time
70 ns
(C
L
: 30 pF)
100 ns
(C
L
: 100 pF)
Power consumption
10
µA
(Standby)
30 mA
(Read operation)
15 mA
(Program/Erase operations)
Package
TC58FVT321/B321FT:
TSOPI48-P-1220-0.50 (weight: 0.51 g)
TC58FVT321/B321XB:
P-TFBGA56-0710-0.80AZ (weight: 0.125 g)
•
000630EBA1
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
•
The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document
shall be made at the customer’s own risk.
•
The products described in this document are subject to the foreign exchange and foreign trade laws.
•
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
•
The information contained herein is subject to change without notice.
2002-08-06 1/48
TC58FVT321/B321FT/XB-70,-10
PIN ASSIGNMENT
(TOP VIEW)
…
TC58FVT321/B321FT
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PIN NAMES
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V
SS
CE
A0
A-1, A0~A20
DQ0~DQ15
CE
OE
Address Input
Data Input/Output
Chip Enable Input
Output Enable Input
Word/Byte Select Input
Write Enable Input
Ready/Busy Output
Hardware Reset Input
Write Protect /
Program Acceleration Input
Not Connected
Power Supply
Ground
BYTE
WE
RY/BY
RESET
WP/ACC
NC
V
DD
V
SS
PIN ASSIGNMENT
(TOP VIEW)
…
TC58FVT321/B321XB
1
A
B
C
D
E
F
G
H
J
K
L
M
NC
NC
NC
NC
A3
A4
A2
A1
A0
CΕ
OE
V
SS
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
2
3
4
5
6
7
8
NC
NC
RY/BY
WP/ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
WE
RESET
NC
A19
DQ5
DQ12
V
DD
DQ4
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A13
A12
A14
A15
A16
BYTE
DQ15
V
SS
NC
NC
2002-08-06 2/48
TC58FVT321/B321FT/XB-70,-10
BLOCK DIAGRAM
V
DD
V
SS
RY/BY
DQ0
DQ15
RY/BY Buffer
I/O Buffer
WP/ACC
WE
BYTE
RESET
CE
OE
Control Circuit
Data Latch
Command Register
Memory Cell
Array
Memory Cell
Array
Memory Cell
Array
Bank 0
Bank 7
Bank 8
A0
Address Buffer
Address Latch
A20
A-1
2002-08-06 3/48
TC58FVT321/B321FT/XB-70,-10
MODE SELECTION
BYTE MODE WORD MODE
MODE
Read
ID Read (Manufacturer Code)
ID Read (Device Code)
Standby
Output Disable
Write
Block Protect 1
Verify Block Protect
Temporary Block Unprotect
Hardware Reset / Standby
Boot Block Protect
CE
OE
(1)
WE
H
H
H
*
H
(2)
(2)
A9
A9
V
ID
V
ID
*
*
A9
V
ID
V
ID
*
*
*
A6
A6
L
L
*
*
A6
L
L
*
*
*
A1
A1
L
L
*
*
A1
H
H
*
*
*
A0
A0
L
H
*
*
A0
L
L
*
*
*
RESET
WP/ACC
DQ0~DQ7
D
OUT
Code
Code
High-Z
High-Z
D
IN
*
Code
*
High-Z
*
DQ0~DQ15
D
OUT
Code
Code
High-Z
High-Z
D
IN
*
Code
*
High-Z
*
L
L
L
H
*
L
L
L
*
*
*
L
L
L
*
H
H
V
ID
L
*
*
*
H
H
H
H
*
H
H
H
V
ID
L
*
*
*
*
*
*
*
*
*
*
*
L
H
*
*
*
Notes:
*
=
V
IH
or V
IL
, L
=
V
IL
, H
=
V
IH
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.
Addresses are A20~A0 in Word Mode ( BYTE
=
V
IH
), A20~A-1 in Byte Mode ( BYTE
=
V
IL
).
(2) Pulse input
ID CODE TABLE
CODE TYPE
Manufacturer Code
TC58FVT321
Device Code
TC58FVB321
Verify Block Protect
*
BA
(2)
A20~A12
*
*
A6
L
L
L
L
A1
L
L
L
H
A0
L
H
H
L
CODE (HEX)
0098H
009AH
009CH
Data
(3)
(1)
Notes:
*
=
V
IH
or V
IL
, L
=
V
IL
, H
=
V
IH
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.
(2) BA: Block Address
(3) 0001H - Protected Block
0000H - Unprotected Block
2002-08-06 4/48
TC58FVT321/B321FT/XB-70,-10
COMMAND SEQUENCES
BUS
COMMAND
SEQUENCE
WRITE
CYCLES
REQ’D
Read/Reset
Read/Reset
Word
Byte
Word
ID Read
Byte
Word
Byte
Program Suspend
Program Resume
Auto Chip
Erase
Auto Block
Erase
Word
Byte
Word
Byte
1
1
4
Word
3
Byte
Fast Program
Set
Fast Program
Fast Program Reset
Hidden ROM
Mode Entry
Hidden ROM
Program
Hidden ROM
Erase
Hidden ROM
Mode Exit
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
2
Byte
4
6
4
Word
Byte
2
2
3
AAAH
555H
AAAH
XXXH
XXXH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
BK
(3)
FIRST BUS
WRITE CYCLE
Addr.
XXXH
555H
AAAH
555H
Data
F0H
AAH
SECOND BUS
WRITE CYCLE
Addr.
Data
THIRD BUS
WRITE CYCLE
Addr.
Data
FOURTH BUS
WRITE CYCLE
Addr.
Data
FIFTH BUS
WRITE CYCLE
Addr.
Data
SIXTH BUS
WRITE CYCLE
Addr.
Data
1
3
2AAH
555H
2AAH
55H
555H
AAAH
BK
(3)
F0H
RA
(1)
RD
(2)
+
+
90H
IA
(4)
3
AAAH
555H
AAAH
1
1
6
BK
BK
(3)
(3)
AAH
555H
2AAH
555H
B0H
30H
AAH
2AAH
555H
AAH
B0H
30H
60H
BPA
(9)
55H
555H
BK
(3)
ID
(5)
AAAH
55H
555H
AAAH
A0H
PA
(6)
Auto-Program
4
AAH
PD
(7)
555H
AAAH
55H
555H
AAAH
80H
555H
AAAH
AAH
2AAH
555H
55H
555H
AAAH
10H
6
555H
AAAH
BK
BK
(3)
(3)
2AAH
555H
55H
555H
AAAH
80H
555H
AAAH
AAH
2AAH
555H
55H
BA
(8)
30H
Block Erase Suspend
Block Erase Resume
Block Protect 2
XXXH
555H
60H
XXXH
BK
(3)
40H
BPA
(9)
BPD
(10)
Verify Block
Protect
2AAH
AAH
555H
2AAH
555H
A0H
90H
AAH
PA
(6)
+
+
90H
BPA
(9)
55H
555H
BK
(3)
BPD
(10)
AAAH
55H
PD
F0H
(7)
3
AAH
555H
AAAH
20H
XXXH
2AAH
555H
(13)
55H
555H
AAAH
88H
(6)
(7)
AAH
2AAH
555H
55H
555H
AAAH
A0H
PA
PD
AAH
2AAH
555H
55H
555H
AAAH
80H
555H
AAAH
AAH
2AAH
555H
55H
BA
(8)
30H
AAH
2AAH
555H
55H
555H
AAAH
90H
XXXH
00H
+
+
98H
CA
(11)
Query
Command
55H
BK
(3)
CD
(12)
AAH
Notes: The system should generate the following address patterns:
Word Mode: 555H or 2AAH on address pins A10~A0
Byte Mode: AAAH or 555H on address pins A10~A-1
DQ8~DQ15 are ignored in Word Mode.
(1) RA: Read Address
(2) RD: Read Data
(3) BK: Bank Address
=
A20~A15
(4) IA: Bank Address and ID Read Address (A6, A1, A0)
Bank Address
=
A20~A15
Manufacturer Code
=
(0, 0, 0)
Device Code
=
(0, 0, 1)
(5) ID: ID Data
(6) PA: Program Address
(7) PD: Program Data
(8) BA: Block Address
=
A20~A12
(9) BPA: Block Address and ID Read Address (A6, A1, A0)
Block Address
=
A20~A12
ID Read Address
=
(0, 1, 0)
(10) BPD: Verify Data
(11) CA: CFI Address
(12) CD: CFI Data
(13) F0H: 00H is valid too
2002-08-06 5/48
