TC58NVG1S3ETAI0
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2 GBIT (256M
×
8 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58NVG1S3E is a single 3.3V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E
2
PROM) organized as (2048
+
64) bytes
×
64 pages
×
2048blocks.
The device has two 2112-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes
+
4 Kbytes: 2112 bytes
×
64 pages).
The TC58NVG1S3E is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
2
FEATURES
•
Organization
Memory cell array
Register
Page size
Block size
•
x8
2112
×
128K
×
8
2112
×
8
2112 bytes
(128K
+
4K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 2008 blocks
Max 2048 blocks
Power supply
V
CC
=
2.7V to 3.6V
Access time
Cell array to register
Serial Read Cycle
Program/Erase time
Auto Page Program
Auto Block Erase
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
25
μs
max
25 ns min (CL=100pF)
300
μs/page
typ.
2.5 ms/block typ.
30 mA max.
30 mA max
30 mA max
50
μA
max
•
•
•
•
•
•
•
Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
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2012-09-01C
TC58NVG1S3ETAI0
PIN ASSIGNMENT (TOP VIEW)
TC58NVG1S3ETAI0
×
8
×
8
NC
NC
NC
NC
NC
NC
RY / BY
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
PIN NAMES
I/O1 to I/O8
I/O port
CE
WE
RE
CLE
ALE
WP
RY/BY
V
CC
V
SS
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Power supply
Ground
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2012-09-01C
TC58NVG1S3ETAI0
BLOCK DIAGRAM
V
CC
V
SS
Status register
I/O1
to
I/O8
I/O
Control circuit
Address register
Column buffer
Column decoder
Command register
Data register
Sense amp
Row address decoder
CE
CLE
ALE
WE
RE
WP
Logic control
Control circuit
Row address buffer
decoder
Memory cell array
RY / BY
RY / BY
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
V
IN
V
I/O
P
D
T
SOLDER
T
STG
T
OPR
Power Supply Voltage
Input Voltage
Input /Output Voltage
Power Dissipation
Soldering Temperature (10 s)
Storage Temperature
Operating Temperature
RATING
VALUE
−
0.6 to 4.6
−
0.6 to 4.6
−
0.6 to V
CC
+
0.3
UNIT
V
V
V
W
°C
°C
°C
(
≤
4.6 V)
0.3
260
−
55 to 150
-40 to 85
CAPACITANCE
*(Ta
=
25°C, f
=
1 MHz)
SYMB0L
C
IN
C
OUT
*
PARAMETER
Input
Output
CONDITION
V
IN
=
0 V
V
OUT
=
0 V
MIN
⎯
⎯
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not tested for every device.
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2012-09-01C
TC58NVG1S3ETAI0
VALID BLOCKS
SYMBOL
N
VB
NOTE:
PARAMETER
Number of Valid Blocks
MIN
2008
TYP.
⎯
MAX
2048
UNIT
Blocks
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP.
⎯
MAX
UNIT
V
CC
Power Supply Voltage
2.7
3.6
V
V
IH
High Level input Voltage
2.7 V
≤
V
CC
≤
3.6 V
Vcc x 0.8
⎯
V
CC
+
0.3
V
V
IL
*
Low Level Input Voltage
−
2 V (pulse width lower than 20 ns)
2.7 V
≤
V
CC
≤
3.6 V
−
0.3
*
⎯
Vcc x 0.2
V
DC CHARACTERISTICS
(Ta
=
-40 to 85℃, V
CC
=
2.7 to 3.6V)
SYMBOL
I
IL
I
LO
I
CCO1
I
CCO2
I
CCO3
I
CCS
PARAMETER
Input Leakage Current
Output Leakage Current
Serial Read Current
Programming Current
Erasing Current
Standby Current
CONDITION
V
IN
=
0 V to V
CC
V
OUT
=
0 V to V
CC
CE
=
V
IL
, I
OUT
=
0 mA, tcycle
=
25 ns
⎯
⎯
MIN
⎯
⎯
⎯
⎯
⎯
⎯
TYP.
⎯
⎯
⎯
⎯
⎯
⎯
MAX
±
10
±
10
UNIT
μ
A
μ
A
30
30
30
50
mA
mA
mA
μ
A
CE
=
V
CC
−
0.2 V, WP
=
0 V/V
CC
V
OH
High Level Output Voltage
I
OH
= −
0.1 mA
Vcc – 0.2
⎯
⎯
V
V
OL
Low Level Output Voltage
I
OL
=
0.1 mA
⎯
⎯
0.2
V
I
OL
( RY / BY )
Output current of RY / BY
V
OL
=
0.2 V
pin
⎯
4
⎯
mA
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2012-09-01C
TC58NVG1S3ETAI0
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
=
-40 to 85℃, V
CC
=
2.7 to 3.6V)
SYMBOL
t
CLS
t
CLH
t
CS
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
t
WC
t
WH
t
WW
t
RR
t
RW
t
RP
t
RC
t
REA
tCEA
PARAMETER
CLE Setup Time
CLE Hold Time
MIN
12
5
20
5
12
12
5
12
5
25
10
100
20
20
12
25
⎯
⎯
MAX
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
CE
Setup Time
CE
Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time
CE Access Time
CLE Low to RE Low
ALE Low to RE Low
RE High to Output Hold Time
RE Low to Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
CE High to ALE or CLE Don’t Care
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE High to WE Low
WE High to
CE
Low
WE High to RE Low
Memory Cell Array to Starting Address
Data Cache Busy in Read Cache (following 31h and
3Fh)
20
25
⎯
⎯
⎯
⎯
t
CLR
t
AR
t
RHOH
t
RLOH
t
RHZ
t
CHZ
t
CSD
t
REH
t
IR
t
RHW
t
WHC
t
WHR
t
R
10
10
22
5
⎯
⎯
60
20
⎯
⎯
⎯
⎯
⎯
⎯
0
10
0
30
30
60
⎯
⎯
25
t
DCBSYR1
30
t
DCBSYR2
t
WB
t
RST
Data Cache Busy in Page Copy (following 3Ah)
WE High to Busy
Device Reset Time (Ready/Read/Program/Erase)
⎯
⎯
⎯
35
100
6/6/10/500
μ
s
ns
μ
s
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
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2012-09-01C
