TC74VCX16600FT
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VCX16600FT
Low-Voltage 18-Bit Universal Bus Transceiver with 3.6-V Tolerant Inputs and Outputs
The TC74VCX16600FT is a high performance CMOS 18-bit
universal bus transceiver. Designed for use in 1.8-V, 2.5-V or
3.3-V systems, it achieves high-speed operation while
maintaining the CMOS low power dissipation.
It is also designed with overvoltage tolerant inputs and outputs
up to 3.6 V.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and clock
(CKAB and CKBA) inputs. The clock can be controlled by the
clock-enable (CKENAB and CKENBA) inputs.
Weight: 0.25 g (typ.)
For A-to-B data flow, the device operates in the transparent
mode when LEAB is high. When LEAB is low, the A data is
latched if CKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on
the high-to-low transition of CKAB.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CKBA, and CKENBA.
When the OE input is high, the outputs are in a high-impedance state. This device is designed to be used with
3-state memory address drivers, etc.
All inputs are equipped with protection circuits against static discharge.
Features (Note)
•
•
Low-voltage operation: V
CC
= 1.8 to 3.6 V
High-speed operation: t
pd
= 2.9 ns (max) (V
CC
= 3.0 to 3.6 V)
: t
pd
= 3.7 ns (max) (V
CC
= 2.3 to 2.7 V)
: t
pd
= 7.8 ns (max) (V
CC
= 1.8 V)
•
Output current : I
OH
/I
OL
= ±24 mA (min) (V
CC
= 3.0 V)
: I
OH
/I
OL
= ±18 mA (min) (V
CC
= 2.3 V)
: I
OH
/I
OL
= ±6 mA (min) (V
CC
= 1.8 V)
•
•
•
•
•
Latch-up performance:
−300
mA
ESD performance: Machine model
≥ ±200
V
Human body model
≥ ±2000
V
Package: TSSOP
Bidirectional interface between 2.5 V and 3.3 V signals.
3.6-V tolerant function and power down-protection provided on all inputs and outputs
Note:
Do not apply a signal to any bus pins when it is in the output mode. Damage may result.
All floating (high impedance) bus pins must have their input level fixed by means of pull-up or pull-down
resistors.
Start of commercial production
1997-11
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TC74VCX16600FT
Pin Assignment
(top view)
OEAB
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CKENAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
CKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CKBA
CKENBA
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
V
CC
22
A16 23
A17 24
GND 25
A18 26
OEBA
27
LEBA 28
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TC74VCX16600FT
Truth Table
(A bus
→
B bus)
Inputs
CKENAB
X
X
X
H
H
L
L
L
L
OEAB
H
L
L
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
L
L
CKAB
X
X
X
X
X
A
X
L
H
X
X
L
H
Outputs
B
Z
L
H
B0
(Note 2)
B0
(Note 2)
L
H
B0
(Note 1)
B0
(Note 1)
H
L
X
X
Note 1: Output level before the indicated steady-state input conditions were established, provided that
CKBA
was
low or high before LEBA went low.
Note 2: Output level before the indicated steady-state input conditions were established, provided that
CKENAB
was low or high before LEAB went low.
Truth Table
(B bus
→
A bus)
Inputs
CKENBA
X
X
X
H
H
L
L
L
L
OEBA
H
L
L
L
L
L
L
L
L
LEBA
X
H
H
L
L
L
L
L
L
CKBA
X
X
X
X
X
B
X
L
H
X
X
L
H
Outputs
A
Z
L
H
A0
(Note 2)
A0
(Note 2)
L
H
A0
(Note 1)
A0
(Note 1)
H
L
X
X
Note 1: Output level before the indicated steady-state input conditions were established, provided that
CKBA
was
low or high before LEBA went low.
Note 2: Output level before the indicated steady-state input conditions were established, provided that
CKENAB
was low or high before LEAB went low.
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TC74VCX16600FT
System Diagram
OEAB
1
29
CKENBA
30
CKBA
LEBA
OEBA
CKENAB
28
27
56
55
CKAB
LEAB
2
LE
LE
D
54
B1
A1
3
D
LE
D
LE
D
To 17 other channels
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TC74VCX16600FT
Absolute Maximum Ratings (Note 1)
Characteristics
Power supply voltage
DC input voltage
( OEAB , OEBA , LEAB,
LEBA, CKAB , CKBA ,
CKENAB , CKENBA )
V
IN
−
0.5 to 4.6
Symbol
V
CC
Rating
−
0.5 to 4.6
Unit
V
V
−
0.5 to 4.6 (Note 2)
DC bus I/O voltage
V
I/O
I
IK
I
OK
I
OUT
P
D
I
CC
/I
GND
T
stg
−
0.5 to V
CC
+
0.5
V
(Note 3)
Input diode current
Output diode current
DC output current
Power dissipation
DC V
CC
/ground current per supply pin
Storage temperature
−
50
±
50
±
50
mA
(Note 4)
mA
mA
mW
mA
°C
400
±
100
−
65 to 150
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: OFF state
Note 3: High or low state. I
OUT
absolute maximum rating must be observed.
Note 4: V
OUT
<
GND, V
OUT
>
V
CC
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