1
TC850
15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL
CONVERTER
FEATURES
s
s
s
s
15-bit Resolution Plus Sign Bit
Up to 40 Conversions per Second
12 Conversions per Second Guaranteed
Integrating ADC Technique
— Monotonic
— High Noise Immunity
— Auto-Zeroed Amplifiers Eliminate Offset
Trimming
Wide Dynamic Range ...................................... 96dB
Low Input Bias Current ................................... 30pA
Low Input Noise ........................................... 30
µ
V
P-P
Sensitivity ....................................................... 100
µ
V
Flexible Operational Control
— Continuous or On-Demand Conversions
— Data Valid Output
Bus Compatible, 3-State Data Outputs
— 8-Bit Data Bus
— Simple
µ
P Interface
— Two Chip Enables
— Read ADC Result Like Memory
±
5V Power Supply Operation ...................... 20mW
40-Pin Dual-in-Line or 44-Pin PLCC Packages
2
GENERAL DESCRIPTION
The TC850 is a monolithic CMOS analog-to-digital
converter (ADC) with resolution of 15-bits plus sign. It
combines a chopper-stabilized buffer and integrator with a
unique multiple-slope integration technique that increases
conversion speed. The result is 16 times improvement in
speed over previous 15-bit, monolithic integrating ADCs
(from 2.5 conversions per sec up to 40 per sec). Faster
conversion speed is especially welcome in systems with
human interface, such as digital scales.
The TC850 incorporates an ADC and a
µP-compatible
digital interface. Only a voltage reference and a few noncriti-
cal passive components are required to form a complete 15-
bit plus sign ADC.
CMOS processing provides the TC850 with high-
impedance differential inputs. Input bias current is typically
only 30pA, permitting direct interface to sensors. Input
sensitivity of 100µV per least significant bit (LSB) eliminates
the need for precision external amplifiers. The internal
amplifiers are auto-zeroed, guaranteeing a zero digital output
with 0V analog input. Zero adjustment potentiometers or
calibrations are not required.
The TC850 outputs data on an 8-bit, 3-state bus. Digital
inputs are CMOS compatible; outputs are TTL/CMOS com-
patible. Chip-enable and byte-select inputs combined with
an end-of-conversion output ensures easy interfacing to a
wide variety of microprocessors. Conversions can be per-
formed continuously or on command. In continuous mode,
data is read as three consecutive bytes and manipulation of
address lines is not required.
Operating from
±5V
supplies, the TC850 dissipates only
20mW. It is packaged in 40-pin plastic or ceramic dual-in-
line packages (DIPs) and in a 44-pin plastic leaded chip
carrier (PLCC), surface-mount package.
3
s
s
s
s
s
4
s
s
s
5
FUNCTIONAL BLOCK DIAGRAM
REF2
+
REF1
+
39
34
REF
–
36
–
IN
+
–
IN
COMMON
32
31
30
ANALOG
MUX
+
BUF
25
RINT
INT IN
24
CINT
–5V
INT OUT
23
22
40
+5V
6
–
BUFFER
+
INTEGRATOR
–
+
COMPARATOR
TC850
A/D
CONTROL
SEQUENCER
6-BIT
UP/DOWN
COUNTER
9-BIT
UP/DOWN
COUNTER
ORDERING INFORMATION
Part No.
TC850CLW
TC850CPL
TC850IJL
TC850ILW
DATA LATCH
÷4
CLOCK
OSCILLATOR
BUS INTERFACE
DECODE LOGIC
OCTAL 2-INPUT MUX
Package
44-Pin PLCC
40-Pin Plastic DIP
40-Pin CerDIP
44-Pin PLCC
Temperature Range
0°C to +70°C
0°C to +70°C
– 25°C to +85°C
– 25°C to +85°C
7
3-STATE DATA BUS
17
18
5
7
6
3
4
1
2
15
. . . . 8
OSC1
OSC2
CONT/ L/H OVR/ WR
DEMAND
POL
RD
CS
CE
DB0
DB7
8
TC850-4 11/5/96
TELCOM SEMICONDUCTOR, INC.
3-77
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (V
DD
to GND) ....................... +6V
Negative Supply Voltage (V
SS
to GND) ..................... – 9V
Analog Input voltage (IN
+
or IN
–
) ..................... V
DD
to V
SS
Voltage Reference Input
(REF
1+
, REF
1–
, REF
2+
) .............................. V
DD
to V
SS
Logic Input Voltage ................ V
DD
+ 0.3V to GND – 0.3V
Current Into Any Pin .................................................10mA
While Operating ................................................100µA
Ambient Operating Temperature Range
C Device ................................................ 0°C to +70°C
I Device ............................................. – 25°C to +85°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
Package Power Dissipation (T
A
≤
70°C)
CerDIP ..............................................................2.29W
Plastic DIP ........................................................ 1.23W
Plastic PLCC .................................................... 1.23W
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS:
V
S
=
±5V,
f
CLK
= 61.44 kHz, V
FS
= 3.2768V, T
A
= 25°C, Fig. 1 Test Circuit,
unless otherwise specified.
Symbol Parameter
Zero-Scale Error
End Point Linearity Error
Differential Nonlinearity
Input Leakage Current
Test Conditions
V
IN
= 0V
–V
FS
≤
V
IN
≤
+V
FS
V
IN
= 0V, T
A
= 25°C
0°C
≤
T
A
≤
+70°C
– 25°
≤
T
A
≤
+85°C
Over Operating Temperature Range
V
IN
= 0V, V
CM
=
±1V
External Ref Temperature
Coefficient = 0 ppm/°C
0°C
≤
T
A
≤
+70°C
V
IN
= 0V
0°C
≤
T
A
≤
+70°C
V
IN
=
±3.275V
Not Exceeded 95% of Time
Min
—
—
—
—
—
V
SS
+ 1.5
—
—
—
—
—
—
—
3.5
—
—
3.5
—
—
—
—
—
—
—
—
—
—
—
Typ
±0.25
±1
±0.1
30
—
1.1
—
80
2
0.3
0.5
30
2
2
4.9
0.15
0.1
2.3
2.1
4
14
140
1
15
230
190
250
210
140
Max
±0.5
±2
±0.5
75
—
3
V
DD
– 1.5
—
5
2
2
—
3.5
3.5
—
0.4
1
—
1
—
—
—
—
—
450
450
450
450
300
Unit
LSB
LSB
LSB
pA
nA
V
dB
ppm/°C
µV/°C
LSB
µV
P-P
mA
mA
V
V
µA
V
V
µA
µA
µA
pF
pF
nsec
nsec
nsec
nsec
nsec
I
IN
V
CMR
CMRR
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Full-Scale Gain Temperature
Coefficient
Zero-Scale Error
Temperature Coefficient
Full-Scale Magnitude
Symmetry Error
Input Noise
Positive Supply Current
Negative Supply Current
Output High Voltage
Output Low Voltage
Output Leakage Current
Input High Voltage
Input Low Voltage
Input Pull-Up Current
Input Pull-Down Current
Oscillator Output Current
Input Capacitance
Output Capacitance
Chip-Enable Access Time
Read-Enable Access Time
Data Hold From CS or CE
Data Hold From RD
OVR/POL Data Access Time
e
N
I
S +
I
S –
V
OH
V
OL
I
OP
V
IH
IL
I
PU
I
PD
I
OSC
C
IN
C
OUT
t
CE
t
RE
t
DHC
t
DHR
t
OP
3-78
I
O
= 500
µA
I
O
= 1.6 mA
Pins 8 – 15, High-Impedance State
Note 3
Note 3
Pins 2, 3, 4, 6, 7; V
IN
= 0V
Pins 1, 5; V
IN
= 5V
Pin 18, V
OUT
= 2.5V
Pins 1 – 7, 17
Pins 8 – 15, High-Impedance State
CS or CE, RD = LOW (Note 1)
CS = HIGH, CE = LOW (Note 1)
RD = LOW (Note 1)
CS = HIGH, CE = LOW (Note 1)
CS = HIGH, CE = LOW, RD = LOW (Note 1)
TELCOM SEMICONDUCTOR, INC.
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
ELECTRICAL CHARACTERISTICS
(Cont.)
Symbol
t
LH
t
WRE
t
WRD
t
WWR
1
Parameter
Low/High Byte Access Time
Clock Setup Time
RD Minimum Pulse Width
RD Minimum Delay Time
WR Minimum Pulse Width
Clock Setup Time
Test Conditions
CS = HIGH, CE = LOW, RD = LOW (Note 1)
Positive or Negative Pulse Width
CS = HIGH, CE = LOW (Note 2)
CS = HIGH, CE = LOW (Note 2)
CS = HIGH, CE = LOW, Demand Mode
Positive or Negative Pulse Width
Min
—
100
450
150
75
100
Typ
140
—
230
50
25
—
Max
300
—
—
—
—
—
Unit
nsec
nsec
nsec
nsec
nsec
nsec
2
NOTES:
1. Demand mode, CONT/DEMAND = LOW. Figure 10 timing diagram. C
L
= 100pF.
2. Continuous mode, CONT/DEMAND = HIGH. Figure 12 timing diagram.
3. Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to V
CC
are
recommended.
3
PIN CONFIGURATIONS
4
CS
CE
WR
RD
CONT/DEMAND
OVR/POL
L/H
DB7
DB6
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
31
VDD
+
REF1
+
CREF1
–
CREF1
REF –
–
CREF2
+
CREF2
+
REF2
IN+
IN–
CONT/DEMAND
6
5
4
3
2
1
VDD
+
REF1
+
CREF1
–
CREF1
REF –
44
43
42
41
40
WR
RD
NC
CE
CS
OVR/POL
7
L/H
8
39
CREF2
38
CREF2
37
REF2
36
IN+
35
IN–
–
5
+
DB7
9
DB6
10
DB5
11
NC
12
DB4
13
DB3
14
DB2
15
DB1
16
DB0
17
18 19
20
21
22
23
24
25
+
DB5 10
DB4 11
DB3 12
DB2 13
DB1 14
DB0 15
BUSY 16
OSC1 17
OSC2 18
TEST 19
GND 20
TC850CPL
TC850IJL
30 COMMON
29 CINTB
28 CINTA
27 CBUFA
26 CBUFB
25 BUFFER
24
23
22
INTIN
INTOUT
VSS
TC850CLW
TC850ILW
34
NC
33
COMMON
32
CINTB
31
CINTA
30
CBUFA
29
CBUFB
26
27
28
6
INTOUT
21 COMP
NC = NO INTERNAL CONNECTION
BUFFER
COMP
7
OSC1
BUSY
TEST
OSC2
NC
INTIN
GND
VSS
8
TELCOM SEMICONDUCTOR, INC.
3-79
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
PIN DESCRIPTIONS
40-Pin DIP
Pin No.
1
2
3
4
5
6
Symbol
CS
CE
WR
RD
CONT/DEMAND
OVR/POL
Description
Chip select, active HIGH. Logically ANDed with CE to enable read and write inputs. (See
note 4.)
Chip enable, active LOW. (See note 5.)
Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and in demand
mode (CONT/DEMAND = LOW), a logic LOW on WR starts a conversion. (See note 4.)
Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD enables the
3-state data outputs. (See note 5.)
Conversion control input. When CONT/DEMAND = LOW, conversions are initiated by the WR
input. When CONT/DEMAND = HIGH, conversions are performed continuously. (See note 4.)
Overrange/polarity data-select input. When making conversions in the demand mode (CONT/
DEMAND = LOW), OVR/POL controls the data output on DB7 when the high-order byte is
active. (See note 5.)
Low/high byte-select input. When CONT/DEMAND = LOW, this input controls whether low-
byte or high-byte data is enabled on DB0 through DB7. (See note 5.)
Most significant data bit output. When reading the A/D conversion result, the polarity,
overrange, and DB7 data are output on this pin. (See text.)
Data outputs DB6–DB0. 3-state, bus compatible.
A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the deintegrate
phase and goes LOW when conversion is complete. The falling edge of BUSY can be used to
generate a
µP
interrupt.
Crystal oscillator connection or external oscillator input.
Crystal oscillator connection.
For factory testing purposes only. Do not make external connection to this pin.
Digital ground connection.
Connection for comparator auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Negative power supply connection, typically – 5V.
Output of the integrator amplifier. Connect to C
INT
.
Input to the integrator amplifier. Connect to summing node of R
INT
and C
INT
.
Output of the input buffer. Connect to R
INT
.
Connection for buffer auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Connection to buffer auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Connection for integrator auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Connection for integrator auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Analog common.
Negative differential analog input.
Analog common.
Positive input for reference voltage V
REF2
. (V
REF2
= V
REF1
/64)
Positive connection for V
REF2
reference capacitor.
Negative connection for V
REF2
reference capacitor.
Negative input for reference voltages.
Negative connection for V
REF1
reference capacitor.
Positive connection for V
REF1
reference capacitor.
Positive input for V
REF1
.
Positive power supply connection, typically +5V.
7
8
9 – 15
16
L/H
DB7
DB6–DB0
BUSY
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
30
33
34
35
36
37
38
39
40
OSC
1
OSC
2
TEST
DGND
COMP
V
SS
INT
OUT
INT
IN
BUFFER
C
BUFB
C
BUFA
C
INTA
C
INTB
COMMON
IN
–
COMMON
REF
2+
C
REF2+
C
REF2–
REF
–
C
REF1–
C
REF1+
REF
1+
V
DD
NOTES:
4. This pin incorporates a pull-down resistor to DGND.
5. This pin incorporates a pull-up resistor to V
DD
.
3-80
TELCOM SEMICONDUCTOR, INC.
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
THEORY OF OPERATION
The TC850 is a multiple-slope, integrating analog-to-
digital converter (ADC). The multiple-slope conversion pro-
cess, combined with chopper-stabilized amplifiers, results
in a significant increase in ADC speed, while maintaining
very high resolution and accuracy.
1
Multiple-Slope Conversion Principles
One limitation of the dual-slope measurement tech-
nique is conversion speed. In a typical dual-slope method,
the auto-zero and integrate times are each one-half of the
deintegrate time. For a 15-bit conversion, 2
14
+ 2
14
+ 2
15
(65,536) clock pulses are required for auto-zero, integrate,
and deintegrate phases, respectively. The large number of
clock cycles effectively limits the conversion rate to about
2.5 conversions per second, when a typical analog CMOS
fabrication process is used.
The TC850 uses a multiple-slope conversion technique
to increase conversion speed (Figure 2B). This technique
makes use of a two-slope deintegration phase and permits
15-bit resolution up to 40 conversions per second.
During the TC850's deintegration phase, the integration
capacitor is rapidly discharged to yield a resolution of 9 bits.
At this point, some charge will remain on the capacitor. This
remaining charge is then slowly deintegrated, producing an
+5V
–5V
2
Dual-Slope Conversion Principles
The conventional dual-slope converter measurement
cycle (shown in Figure 2A) has two distinct phases:
(1) Input signal integration
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period, measured by counting clock pulses. An oppo-
site polarity constant reference voltage is then integrated
until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, complete conversion
requires the integrator output to "ramp-up" and "ramp-
down." Most dual-slope converters add a third phase, auto-
zero. During auto-zero, offset voltages of the input buffer,
integrator, and comparator are nulled, thereby eliminating
the need for zero-offset adjustments.
Dual-slope converter accuracy is unrelated to the inte-
grating resistor and capacitor values, as long as they are
stable during a measurement cycle. By converting the
unknown analog input voltage into an easily-measured
function of time, the dual-slope converter reduces the need
for expensive, precision passive components.
Noise immunity is an inherent benefit of the integrating
conversion method. Noise spikes are integrated, or aver-
aged, to zero during the integration period. Integrating ADCs
are immune to the large conversion errors that plague
successive approximation converters in high-noise environ-
ments.
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
1
RC 0
3
4
40
V
DD
16 BUSY
8 DB7
9 DB6
10 DB5
11 DB4
12 DB3
13 DB2
14
15
1
2
3
4
5
6
7
17
61.44 kHz
**
18
OSC2
COMP
20
DGND
22
V
SS
+ 32
IN
–
IN
100 MΩ
0.01
µF
INPUT
+1.6384V
DB1
DB0
CS
CE
WR
RD
CONT/DEMAND
OVR/POL
L/H
OSC1
31
COMMON 30
+
REF1 39
+ 33
REF2
36
REF–
+
CREF1 38
TC850
–
CREF1 37
+
CREF2 34
–
CREF2 35
BUFFER
INTIN
INTOUT
25
24
23
5
+0.0265V
1
µF
*
1
µF
*
120 MΩ
RINT
0.1µF
CINT
6
TEST
19
NC
∫
t
SI
V
IN
(t) dt =
V
R
t
RI
,
RC
**
21
CINTA CINTBCBUFA CBUFB
28
0.1
µF
0.1
µF
29
0.1
µF
27
0.1
µF
26
0.1
µF
7
where: V
R
= Reference voltage
t
SI
= Signal integration time (fixed)
t
RI
= Reference voltage integration time (variable).
NOTES:
Unless otherwise specified, all 0.1µF capacitors are film dielectric.
Ceramic capacitors are not recommended.
NC = No internal capacitors
*Polypropylene capacitors.
** 100pF Mica capacitors.
Figure 1. Standard Circuit Configuration
8
3-81
TELCOM SEMICONDUCTOR, INC.
RF/无线
