TDA19989
150 MHz pixel rate HDMI 1.3 transmitter with 3
×
8-bit video
inputs, HDCP and CEC support
Rev. 01 — 15 February 2010
Preliminary data sheet
1. General description
TDA19989 is a very low power and very small size High-Definition Multimedia Interface
(HDMI) v. 1.3a transmitter. It is backward compatible DVI 1.0 and can be connected to any
DVI 1.0 and HDMI sink.
This device is primarily intended for mobile applications like Digital Video Camera (DVC),
Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and
Ultra-Mobile Personal Computer (UM PC) where size and very low power are mandatory
for battery autonomy.
It allows mixing 3
×
8-bit RGB or YCbCr video stream with a pixel rate up to 150 MHz
together with one S/PDIF or one I
2
S-bus audio streams with an audio sampling rate up to
192 kHz.
In order to be compatible with most applications, TDA19989 integrates a full
programmable input formatter and color space conversion block. The video input formats
accepted are YCbCr 4 :4 : 4 (up to 3
×
8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2
×
12-bit)
and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1
×
12-bit). In case of ITU656-like
format, the input pixel clock can be made active on one (SDR mode) or both edges (DDR
mode).
TDA19989 includes a HDCP 1.3 compliant cipher block. The HDCP key are stored
internally in a non-volatile OTP memory for maximum security.
This device provides additional embedded feature like CEC (Consumer Electronic
Control). CEC is a single bidirectional wire that transmits CEC commands (like Standby
from remote control) over the home appliance network connected through this wire. This
eliminates the need of any additional device to handle this feature thus improving BOM
(Bill Of Materials) of the whole system and enable the connected devices (CEC enabled)
to be controlled by only one remote control.
TDA19989 supports xvYCC HDMI 1.3a feature.
It can be switched to very low power Standby or Sleep modes to save power when HDMI
is not used.
TDA19989 includes I
2
C-bus master interface for DDC-bus communication for EDID
reading and HDCP purpose.
This device can be controlled or configured via I
2
C-bus interface.
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
I
2
C-BUS
SLAVE
I
2
S-bus
PLL
SERIALIZER
PIXEL, REPETITION
CEC
CEC
AUDIO
S/PDIF
video
RGB
YCbCr
INPUT
FORMATTER
COLOR
SPACE
CONVERTER
HDCP
1.3 cipher
HDMI
ENCODER
SERIALIZER
HMDI
TMDS
link
I
2
C-BUS
MASTER DDC-BUS
001aal264
Fig 1.
TDA19989 high-level block diagram
2. Features
Compliance:
DVI 1.0
HDMI 1.3a
EIA/CEA-861B
CEC (HDMI 1.3)
SimplayHD
HDCP 1.3
Video:
xvYCC HDMI 1.3 feature
Video formats with a pixel rate up to 150 MHz:
RGB 4 : 4 : 4
YCbCr 4 : 4 : 4
YCbCr 4 : 2 : 2 semi-planar
YCbCr 4 : 2 : 2 ITU656
Maximum resolution:
1080p for TV
1600
×
1200 at 60 Hz for PC (UXGA60)
720p/1080i in ITU656
Programmable color space converter:
RGB to YCbCr
YCbCr to RGB
Programmable input formatter and upsampler/interpolator allows input of any of the
4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656-like formats
Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs
or VREF, HREF and FREF could be used for input data synchronization
Pixel clock input can be made active on one or both edges (selectable by I
2
C-bus)
Repetition of video samples as required by HDMI specification
Audio:
2
×
I
2
S-bus 2 channels and S/PDIF; audio data rate up to 192 kHz per input for
both standards
Deals with multiple levels of HDCP receivers and repeaters
TDA19989_1
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 February 2010
2 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Internal SHA-1 calculation
System operation:
Master DDC-bus interface for EDID read
Controllable via I
2
C-bus
Downstream availability through the use of hot plug detect (HPD) and receiver
detection (RxSense)
Deals with multiple levels of receivers and repeaters
Package:
TFBGA64
Size 4.5
×
4.5
×
0.95 mm
Power management:
External voltage supplies 1.8 V
Low power
Flexible power modes
Miscellaneous:
POR (Power-On Reset)
Audio and video inputs LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant
250 MHz to 1.5 GHz TMDS transmitter operation
3. Applications
Digital Video Camera (DVC)
Digital Still Camera (DSC)
Portable Multimedia Player (PMP)
Mobile Phone
Ultra-Mobile Personal Computer (UM PC)
4. Ordering information
Table 1.
Ordering information
Package
Name
TDA19989AET
TFBGA64
Description
Version
plastic thin fine-pitch ball grid array package; 64 balls SOT962-3
Type number
TDA19989_1
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 February 2010
3 of 47
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Preliminary data sheet
Rev. 01 — 15 February 2010
© NXP B.V. 2010. All rights reserved.
TDA19989_1
5. Block diagram
NXP Semiconductors
AUDIO PROCESSING
ACLK
AUDIO
CAPTURE
PROCESSING
CTS/N
FIFO
BUFFER
HDMI PACKET INSERTION
AUDIO CONTENT
DATA
ISLAND
PACKET
INSERTION
TDA19989
TMDS BLOCK
RxSense
TXC+
AP1
INFO FRAME
WS
ACR
OTP
MEMORY
KEYS
HDCP
PROCESSING
TXC−
TX0+
HDMI
SERIALIZER
TX0−
TX1+
TX1−
TX2+
TX2−
PLL BLOCK
VCLK
CLOCK
MANAGEMENT
NULL AND ACP
VHREF GENERATOR
DOWNSAMPLER
(1)
4 : 4 : 4 to 4 : 2 : 2
3
×
8-bit RGB or YCbCr 4 : 4 : 4
2
×
12-bit YCbCr 4 : 4 : 2 semi-planar
VIDEO
INPUT
DATA
CAPTURE
I
2
C-BUS/DDC-BUS
INTERFACE
REGISTERS
UPSAMPLER
4:2:2
to
4:4:4
VIDEO PROCESSING
COLOR SPACE
CONVERTER
(1)
YCbCr to RGB
RGB to YCbCr
INTERRUPT
GENERATION
EXT_SWING
HDMI 1.3 transmitter with HDCP and CEC support
VSYNC/VREF
HSYNC/VREF
DE/FREF
VPA[0] to VPA[7]
VPB[0] to VPB[7]
VPC[0] to VPC[7]
HPD
MANAGEMENT
HPD
INT
DDC-BUS
MASTER
I
2
C-BUS
SLAVE
CEC
CEC
DSCL
DSDA
CSCL
CSDA
001aal260
TDA19989
(1) The color space converter can be bypassed.
The device can handle HDCP based on 1.3 features.
4 of 47
Fig 2.
TDA19989 Block diagram
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
6. Pinning information
6.1 Pinning
TDA19989
ball A1
index area
A
B
C
D
E
F
G
H
001aal266
1
2
3
4
5
6
7
8
Transparent top view
Fig 3.
Pin configuration (TFBGA64)
6.2 Pin description
Table 2.
Symbol
ACLK
AP0
AP1
HPD
EXT_SWING
Pin description
Pin
H5
G5
F5
E6
E7
Type
[1]
I
I
I
I
O
Description
audio clock input
audio port 0 input
audio port 1 input
hot plug detect; 5 V tolerant
TMDS output swing adjustment; place resistor
(R
EXT_SWING
= 10 kΩ
±
1 %) between this pin and analog
ground.
DDC-bus data input/output; 5 V tolerant
DDC-bus clock input; 5 V tolerant
input video pixel clock
input horizontal synchronization or reference input
input vertical synchronization or reference input
data enable or field reference input
I
2
C-bus clock input; 1.8 V to 3.3 V tolerant
I
2
C-bus data input/output; 1.8 V to 3.3 V tolerant
interrupt HDMI output (open-drain); this pin is used as Dual
function pin selectable through I
2
C-bus. In calibration mode
only this pin is used as input for 10 ms
±
1 % calibration pulse.
In operation mode this pin is used to warn the external
microprocessor that a special event has occurred for HDMI or
CEC
negative data channel 0 for TMDS output
positive data channel 0 for TMDS output
negative data channel 1 for TMDS output
© NXP B.V. 2010. All rights reserved.
DSDA
DSCL
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CSCL
CSDA
INT
F6
F7
D4
F4
G4
H4
B5
A5
B6
I/O
I
I
I
I
I
I
I/O
I/O
TX0−
TX0+
TX1−
TDA19989_1
E8
D8
C8
O
O
O
Preliminary data sheet
Rev. 01 — 15 February 2010
5 of 47
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