TDA19998HL
Smart HDMI 1.4a (4 : 1) switch with auto-adaptive equalizer
Rev. 3 — 4 August 2010
Product data sheet
1. General description
The High-Definition Multimedia Interface (HDMI) switch enables connection of multiple
DVI/HDMI inputs to a receiver with at least one input. The TDA19998HL is a switch with
four HDMI 1.4a compliant DVI/HDMI inputs and one DVI/HDMI output. Each HDMI input
has its own dedicated embedded EDID memory. A fifth DDC-bus input is available for
VGA or second HDMI input of SoC. The built-in auto-adaptive equalizer improves signal
quality, allowing the use of cable lengths up to 30 m.
The TDA19998HL supports Deep Color mode in 10-bit and 12-bit per channel up to
1920
×
1080p at 50/60 Hz. The TDA19998HL supports DVI/HDMI streams with or without
High-bandwidth Digital Content Protection (HDCP 1.4) and all Data Island packets.
The TDA19998HL settings are controllable via the I
2
C-bus.
The TDA19998HL, pin compatible with TDA19997, is embedding the "F
3
technology" from
NXP, allowing no delay in switching from one HDMI port to any other HDMI port while
keeping HDMI output stream encrypted.
2. Features and benefits
Complies with the HDMI 1.4a, DVI 1.0, EIA/CEA-861D and HDCP 1.4 standards
Four independent DVI/HDMI inputs, up to 2.25 gigasamples per second
Pin compatible with TDA9996/TDA9995/TDA19997/TDA19995
"F
3
technology" for fast switching HDMI port
Robust auto-adaptive equalizer
up to 20 m AWG26 at 2.25 Gbit/s
up to 30 m AWG24 at 1.5 Gbit/s
Integrated 50
Ω
single-ended termination resistors
+5 V signal detection for each HDMI input
Supports color depth processing at 24-bit, 30-bit or 36-bit per pixel
Supports 3D video formats with all structures and all timings up to 2.25 GHz
Supports all Data Island packets
Activity detection on each input, manages output activity and power consumption
Extended mode: re-generate output TMDS waveform removing jitter and skew
Frequency measurement allowing direct reading of format/resolution
Automatic mode for main features:
Automatic Hot Plug Detect (HPD) generation and termination resistors
management
NXP Semiconductors
TDA19998HL
Smart HDMI 1.4a (4 : 1) switch with auto-adaptive equalizer
Automatic HPD generation with programmable duration
Automatic EDID load
Display Data Channel (DDC) bus:
5 V tolerant, DDC-bus inputs with bit rates up to 400 kbit/s
One DDC-bus output with the same latency as the HDMI stream pipeline delay
DDC-bus master switch functionality avoids bus corruption
DDC-bus level-shifting buffer with digital lock-up protection
A fifth DDC-bus input available for VGA or second HDMI input of SoC
I
2
C-bus controllable at bit rates up to 400 kbit/s
Non-volatile memory for switch management (Hot Plug Detect, Power-down)
Embedded Extended Display Identification Data (EDID) memory:
5 embedded EDID memory supplied by +5 V from HDMI source
253-byte shared and 3-byte of dedicated EDID memory per HDMI input
Non-volatile memory for programming default EDID content
Supports sources without +5 V
An extra 128-byte blocks for DVI or PC formats
EDID update by I
2
C-bus, example for AVR applications
Fail-safe output in Idle mode
Mute pin preventing from pop noise/image noise
ATC/Rx compliant for 36-bit Deep Color 1080p 60 Hz
ATC/Tx eye diagram compliant for 36-bit Deep color 1080p 60 Hz
Programmable slave address
Ready for HDMI Ethernet Audio return Channel (HEAC)
3.3 V and 1.8 V power supplies
Additional ESD protection pin for CEC line
ESD protection:
HBM: class 2
MM: class B
FCDM: class IV
IEC 61000-4-2 class 3 for HDMI inputs
Power-down mode with dedicated pin
CMOS process
Lead (Pb) free LQFP100 14
×
14
×
1 mm package, pitch 0.5 mm
3. Applications
3D-TV
HDTV (plasma, Rear projection TV and LCD TV)
YCbCr or RGB Hi-Speed video digitizer
Projector
Home theater
AVR
Switch box
TDA19998HL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 4 August 2010
2 of 26
NXP Semiconductors
TDA19998HL
Smart HDMI 1.4a (4 : 1) switch with auto-adaptive equalizer
4. Quick reference data
Table 1.
Quick reference data
In accordance with the Absolute Maximum Rating System (IEC 60134). V
DDH(3V3)
= 3.13 V to 3.47 V; V
DDDC(3V3)
= 3.0 V to
3.6 V; V
DDH(1V8)
= 1.65 V to 1.95 V; V
DDDC(1V8)
= 1.65 V to 1.95 V; T
amb
= 0
°
C to +70
°
C; typical values measured at V
DDH(3V3)
and V
DDDC(3V3)
= 3.3 V; V
DDH(1V8)
and V
DDDC(1V8)
= 1.8 V and T
amb
= 25
°
C; f
max
= 2.25 GHz; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
HDMI input pins: RXx_D0+, RXx_D0−, RXx_D1+, RXx_D1−, RXx_D2+, RXx_D2−, RXx_C+, RXx_C−, RXx_HPD,
RXx_5V, RXy_DDC_DAT, RXy_DDC_CLK, CEC
[1][2]
V
ESD
electrostatic discharge voltage
IEC 61000-4-2 class 3 (contact
discharge)
7
-
-
kV
HDMI pins: OUT_D0+, OUT_D0−, OUT_D1+, OUT_D1−, OUT_D2+, OUT_D2−, RXx_D0+, RXx_D0−, RXx_D1+,
RXx_D1−, RXx_D2+, RXx_D2−
[1]
f
max
Supplies
V
DDH(3V3)
V
DDH(1V8)
V
DDS(3V3)
V
DDDC(1V8)
[1]
[2]
maximum frequency
HDMI supply voltage (3.3 V)
HDMI supply voltage (1.8 V)
supervisor supply voltage (3.3 V)
core digital supply voltage (1.8 V)
2.25
3.13
1.65
3.0
1.65
-
3.3
1.8
3.3
1.8
-
3.47
1.95
3.6
1.95
GHz
V
V
V
V
x = A, B, C, D.
y = A, B, C, D, E.
5. Ordering information
Table 2.
Ordering information
Package
Name
Description
Version
SOT407-1
LQFP100 plastic low profile quad flat package; 100 leads;
body 14
×
14
×
1.4 mm
Type number Maximum data rate per
channel
TDA19998HL
2.25 gigasamples per second
TDA19998HL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 4 August 2010
3 of 26
NXP Semiconductors
TDA19998HL
Smart HDMI 1.4a (4 : 1) switch with auto-adaptive equalizer
6. Block diagram
V
DDH(3V3)
TDA19998
V
DDH(1V8)
RXA_C+
RXA_C−
RXA_D0+
RXA_D0−
RXA_D1+
RXA_D1−
RXA_D2+
RXA_D2−
EQ
EQ
OUT_C+
EQ
OUT_C−
RXB_C+
RXB_C−
RXB_D0+
RXB_D0−
RXB_D1+
RXB_D1−
RXB_D2+
RXB_D2−
RXC_C+
RXC_C−
RXC_D0+
RXC_D0−
RXC_D1+
RXC_D1−
RXC_D2+
RXC_D2−
RXD_C+
RXD_C−
RXD_D0+
RXD_D0−
RXD_D1+
RXD_D1−
RXD_D2+
RXD_D2−
OUT_D0+
RT AND EQ
HDMI
SWITCH
OUT_D1+
OUT_D1−
RT AND EQ
OUT_D0−
OUT_D2+
OUT_D2−
RT AND EQ
I
2
C-BUS
INTERRUPT
HP_BIAS
EDID
CONTROL
OSCILLATOR
I2C_SDA
I2C_SCL
INT_N/MUTE
RXA_5V
RXA_HPD
RXA_DDC_DAT
RXA_DDC_CLK
RXB_5V
RXB_HPD
RXB_DDC_DAT
RXB_DDC_CLK
RXC_5V
RXC_HPD
RXC_DDC_DAT
RXC_DDC_CLK
RXD_5V
RXD_HPD
RXD_DDC_DAT
RXD_DDC_CLK
HP_BIAS
HP_BIAS
DDC
BUFFER
MASTER
SWITCH
OUT_DDC
OUT_DDC_DAT
OUT_DDC_CLK
HP_BIAS
REGULATOR
AUX_5V
RXE_DDC_DAT
RXE_DDC_CLK
001aal395
Fig 1.
Block diagram
TDA19998HL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 4 August 2010
4 of 26
NXP Semiconductors
TDA19998HL
Smart HDMI 1.4a (4 : 1) switch with auto-adaptive equalizer
7. Pinning information
7.1 Pinning
100
76
75
1
TDA19998
25
26
50
51
001aal396
Fig 2.
Pin configuration
7.2 Pin description
Table 3.
Symbol
V
SS
OUT_C+
OUT_C−
V
DDO(3V3)
OUT_DDC_CLK
OUT_DDC_DAT
V
SS
V
DDDC(1V8)
RXA_HPD
RXA_5V
RXA_DDC_DAT
RXA_DDC_CLK
RXA_C−
RXA_C+
V
DDH(3V3)
RXA_D0−
RXA_D0+
V
SS
RXA_D1−
RXA_D1+
V
DDH(3V3)
RXA_D2−
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Type
[1]
Description
G
O
O
P
O
I/O
G
P
O
I
I/O
I
I
I
P
I
I
G
I
I
P
I
ground
HDMI output positive clock channel
HDMI output negative clock channel
output supply voltage; 3.3 V
DDC-bus clock output; open-drain; 5 V tolerant
DDC-bus data input/output; open-drain; 5 V tolerant
ground
digital core supply voltage; 1.8 V
HDMI output A Hot Plug Detect; 5 V tolerant
input A HDMI +5 V
HDMI input/output A DDC-bus serial data; open-drain; 5 V
tolerant
HDMI input A DDC-bus serial clock; open-drain; 5 V tolerant
HDMI input A negative clock channel
HDMI input A positive clock channel
HDMI input A supply voltage; 3.3 V
HDMI input A negative data channel 0
HDMI input A positive data channel 0
ground
HDMI input A negative data channel 1
HDMI input A positive data channel 1
HDMI input A supply voltage; 3.3 V
HDMI input A negative data channel 2
TDA19998HL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 4 August 2010
5 of 26
