AN01054
Smart Card Interface using TDA8007BHL/C2/C3
Rev. 1.1 — 27 March 2012
Application note
Document information
Info
Content
Keywords
Abstract
TDA8007BHL/C2, TDA8007BHL/C3, Smart card interface, Protocol
T = 0 and T=1, Double smart card reader, Three smart card reader
This application note is a generic documentation given the basic
rules to use the TDA8007BHL/C2 or C3 and handles a
communication between a system controller and two or three
smart cards.
The TDA8007B functions are controlled by micro-controller
through a parallel interface in both modes, multiplexed and non
multiplexed.
NXP Semiconductors
AN01054
Smart Card Interface using TDA8007BHL/C2/C3
Revision history
Rev
Date
1.1
1.0
20120327
20110707
Description
Fig 9
updated and PRES external resistor calculation added
First version
Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
AN01054
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
Rev. 1.1 — 27 March 2012
2 of 59
NXP Semiconductors
AN01054
Smart Card Interface using TDA8007BHL/C2/C3
1. Introduction
The TDA8007B is a low cost card interface for dual smart card readers. Controlled
through a parallel bus, it takes care of all ISO 7816, EMV and GSM11-11 requirements. It
may be interfaced to the P0/P2 ports of a C51 family micro-controller, and be addressed
as a memory through MOVX instructions. It may also be addressed on a non multiplexed
8 bits data bus, by the means of registers addresses AD0, AD1, AD2 and AD3. The
integrated ISO UART and the timer counters allow easy use even at high baud rates with
no real time constraints. Due to its chip select external I/O and interrupt features, it
simplifies a lot the realization of any number of card readers. It gives the cards and the
reader a very high level of security, due to its special hardware against ESD, short-
circuit, power failure, etc. Its integrated step-up converter allows operation within a
supply voltage range of 2.7 to 6V.
The schematic diagram and the layout for dual cards interface is given as example in
Annex.
2. General description
2.1 Features
•
•
•
•
•
•
•
•
•
Control and communication through an 8 bits parallel interface, compatible with
multiplexed or non multiplexed memory access.
Specific ISO UART with parallel access on I/O for automatic convention processing,
variable baud rate through frequency or ratio programming, error management at
character level for T=0, extra guard time register.
1 to 8 characters FIFO in reception mode.
Automatic activation and deactivation sequence through an independent sequencer.
24 bits timers counter for ATR and waiting time processing.
Current limitation in case of short circuit.
Supply voltage from 2.7 to 6 V
Power down mode for reducing current consumption when no activity.
Manual or automatic character retransmission in case of parity error.
Block diagram of this circuit is presented next page.
AN01054
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
Rev. 1.1 — 27 March 2012
3 of 59
NXP Semiconductors
AN01054
Smart Card Interface using TDA8007BHL/C2/C3
Fig 1.
Block diagram
AN01054
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
Rev. 1.1 — 27 March 2012
4 of 59
NXP Semiconductors
AN01054
Smart Card Interface using TDA8007BHL/C2/C3
2.2 Differences between TDA8007B/C2 and TDA8007B/C3Heading 3
In order to satisfy the new EMV2000 specifications, the TDA8007B/C2 has been
improved.
By the way, the remaining problems seen on the C2 version have been solved.
2.2.1 EMV2000 improvement:
1) Reception at 11,8 etus in T=0, 10,8 in T=1
The TDA8007B/C2 is unable to correctly interpret received characters having a delay
between two consecutive leading edges of the start bit of 11,8 etus (10.8 etu in T=1).
This feature is now possible with the TDA8007B/C3.
2) Windows reception during Answer To Reset
The TDA8007B/C2 has a reception window during ATR which is between 384 and
42,000 CLK. This window does not satisfy the new EMV2000 specification (380-
42000CLK).
The windows reception has been modified and now it is possible to receive properly an
ATR beginning between 380 and 42000 CLK.
2.2.2 TDA8007BC2 problems solved
1) CRED issue
Description:
When CRED bit within the MSR register goes high, 1 (or 2) more card clock cycle should
be left to the UART before taking the value into account.
Modification on the TDA8007B/C3:
This issue is solved with the C3 version so when CRED bit is high, the UART is ready.
AN01054
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
Rev. 1.1 — 27 March 2012
5 of 59
RF/无线
