INTEGRATED CIRCUITS
DATA SHEET
TDA9150B
Programmable deflection controller
Preliminary specification
File under Integrated Circuits, IC02
July 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Programmable deflection controller
FEATURES
General
•
6.75, 13.5 and 27 MHz clock frequency
•
Few external components
•
Synchronous logic
•
I
2
C-bus controlled
•
Easy interfacing
•
Low power
•
ESD protection
•
Flash detection with restart
•
Two-level sandcastle pulse.
Vertical deflection
•
Self adaptive 16-bit precision vertical scan
•
DC coupled deflection to prevent picture bounce
•
Programmable fixed compression to 75%
•
S-correction can be preset
•
S-correction setting independent of the field frequency
•
Differential output for high DC stability
•
Current source outputs for high EMC immunity
•
Programmable de-interlace phase.
East-West correction
•
DC coupled EW correction to prevent picture bounce
•
2nd and 4th order geometry correction can be preset
•
Trapezium correction
•
Geometry correction settings are independent of field
frequency
•
Self adaptive Bult generator prevents ringing of the
horizontal deflection
•
Current source output for high EMC immunity.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
TDA9150B
20
PIN POSITION
DIP
MATERIAL
plastic
Horizontal deflection
•
Phase 2 loop with low jitter
•
Internal loop filter
•
Dual slicer horizontal flyback input
•
Soft start by I
2
C-bus
TDA9150B
•
Over voltage protection/detection with selection and
status bit.
EHT correction
•
Input selection between aquadag or EHT bleeder
•
Internal filter.
GENERAL DESCRIPTION
The TDA9150B is a programmable deflection controller
contained in a 20-pin DIP package and constructed using
BIMOS technology. This high performance
synchronization and DC deflection processor has been
especially designed for use in both digital and analog
based TV receivers and monitors, and serves horizontal
and vertical deflection functions for all TV standards. The
TDA9150B uses a line-locked clock at 6.75, 13.5 or
27 MHz, depending on the line frequency and application,
and requires only a few external components. The device
is self-adaptive for a number of functions and is fully
programmable via the I
2
C-bus.
CODE
SOT146-1
July 1994
2
Philips Semiconductors
Preliminary specification
Programmable deflection controller
QUICK REFERENCE DATA
SYMBOL
V
CC
I
CC
P
tot
T
amb
Inputs
V
14
V
13
V
12
V
5
V
18
V
17
V
PSL
V
1
V
3
V
9
Outputs
V
20
I
11
−I
10(M)
V
10,11
I
6(M)
V
6
V
2
V
2
V
2
V
19
Notes
1. Hard wired to ground or V
CC
is highly recommended.
2. DAC values: vertical amplitude = 31; EHT = 0; SHIFT = 3; SCOR = 0.
horizontal output (HOUT) voltage
(open drain)
vertical differential (VOUT
A, B
)
output current (peak value)
vertical output voltage
EW (EWOUT) total output current I
8
=
−120 µA
(peak value)
EW (EWOUT) output voltage
I
20
= 10 mA
vertical amplitude = 100%;
I
8
=
−120 µA;
note 2
−
440
0
−
1.0
−
−
−
I
19
= 2 mA
0
−
475
−
−
−
0.5
2.5
4.5
−
line-locked clock (LLC) logic level
horizontal sync (H
A
) logic level
vertical sync (V
A
) logic level
line-locked clock select (LLCS)
logic level
serial clock (SCL) logic level
serial data input (SDA) logic level
horizontal flyback (HFB) phase
slicing level
horizontal flyback (HFB) blanking
slicing level
over voltage protection (PROT)
level
EHT flash detection level
FBL = logic 0
FBL = logic 1
note 1
−
−
−
−
−
−
−
−
−
−
−
TTL
TTL
TTL
CMOS 5 V
CMOS 5 V
CMOS 5 V
3.9
1.3
100
3.9
1.5
PARAMETER
supply voltage
supply current
total power dissipation
operating ambient temperature
f
clk
= 6.75 MHz
CONDITIONS
−
−
−25
MIN.
7.2
8.0
27
220
−
TYP.
TDA9150B
MAX.
8.8
−
−
+70
−
−
−
−
−
−
−
−
−
−
−
UNIT
V
mA
mW
°C
V
V
mV
V
V
0.5
510
3.9
930
5.5
−
−
−
V
CC
V
µA
V
µA
V
S
ANDCASTLE OUTPUT LEVELS
(DSC)
base voltage level
horizontal and vertical blanking
voltage level
video clamping voltage level
V
V
V
H
ORIZONTAL OFF
-
CENTRE SHIFT
(
OFCS
)
output voltage
V
July 1994
3
Philips Semiconductors
Preliminary specification
Programmable deflection controller
BLOCK DIAGRAM
TDA9150B
Fig.1 Block diagram.
July 1994
4
Philips Semiconductors
Preliminary specification
Programmable deflection controller
PINNING
SYMBOL
HFB
DSC
PROT
AGND
LLCS
EWOUT
EHT
R
CONV
FLASH
VOUT
B
VOUT
A
V
A
H
A
LLC
DGND
V
CC
SDA
SCL
OFCS
HOUT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
horizontal flyback input
display sandcastle input/output
over voltage protection input
analog ground
line-locked clock selection input
east-west geometry output
EHT compensation
external resistive conversion
flash detection input
vertical output B
vertical output A
vertical information input
horizontal information input
line-locked clock input
digital ground
supply input (+8 V)
serial data input/output
serial clock input
off-centre shift output
horizontal output
TDA9150B
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Input signals (pins 12, 13, 14, 17 and 18)
The TDA9150B requires three signals for minimum
operation (apart from the supply). These signals are the
line-locked clock (LLC) and the two I
2
C-bus signals (SDA
and SCL). Without the LLC the device will not operate
because the internal synchronous logic uses the LLC as
the system clock.
I
2
C-bus transmissions are required to enable the device to
perform its required tasks. Once started the IC will use the
H
A
and/or V
A
inputs for synchronization. If the LLC is not
present the outputs will be switched off and all operations
discarded (if the LLC is not present the line drive will be
inhibited within 2
µs,
the EW output current will drop to
zero and the vertical output current will drop to 20% of the
adjusted value within 100
µs).
The SDA and SCL inputs
meet the I
2
C-bus specification, the other three inputs are
TTL compatible.
The LLC frequency can be divided-by-two internally by
connecting LLCS (pin 5) to ground thereby enabling the
prescaler.
The LLC timing is given in the Chapter “Characteristics”.
July 1994
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