100Gb/s QSFP Transceiver
P
RODUCT
N
UMBER
:TGW-Q14BB-FCQ
Specification
100 - Gbps QSFP28 Pluggable
Optical Transceiver Module
100GBASE-LR4 Pull-Tab
Ordering Information
TGW–Q14BB–FCQ
Model Name
TGW-Q14BB-FCQ
Voltage
3.3V
Category Device type
With DDMI
LWDM DFB
Interface
CML/CML
Temperature
0C~+70C
Distance
10km
Latch Type
Pull TAB
Formerica Optoelectronics Inc
.
5F-11, No.38, Taiyuan St.,Zhubei City,
Hsinchu County 30265, Taiwan
Ph: +886-3-5600286 Fax: +886-3-5600239
Version 01
1.0
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100Gb/s QSFP Transceiver
P
RODUCT
N
UMBER
:TGW-Q14BB-FCQ
Features
Compliant to IEEE 802.3ba and 100GBASE-LR4 standard.
QSFP28 MSA compliant.
Up to 25Gbps data rate per wavelength.
Up to 10km transmission on single mode fiber (SMF).
Operating case temperature: 0~70
oC
.
Maximum 4.0W operation power
LC duplex connector.
RoHS-6 compliant.
Applications
100GBASE-LR4 Ethernet Links
Infiniband QDR and DDR interconnects
Client-side 100G Telecom connections
General Description
This product is a 100Gb/s transceiver module designed for optical communication
applications compliant to 100GBASE-LR4 of the IEEE P802.3ba standard. The module
converts 4 input channels of 25Gb/s electrical data to 4 channels of LAN WDM optical
signals and then multiplexes them into a single channel for 100Gb/s optical transmission.
Reversely on the receiver side, the module de- multiplexes a 100Gb/s optical input into 4
channels of LAN WDM optical signals and then converts them to 4 output channels of
electrical data.
The central wavelengths of the 4 LAN WDM channels are 1295.56, 1300.05, 1304.58 and
1309.14 nm as members of the LAN WDM wavelength grid defined in IEEE 802.3ba. The
high performance cooled LAN WDM EA-DFB transmitters and high sensitivity PIN receivers
provide superior performance for 100Gigabit Ethernet applications up to 10km links and
compliant to optical interface with IEEE802.3ba Clause 88 100GBASE-LR4 requirements.
The product is designed with form factor, optical/electrical connection and digital diagnostic
interface according to the QSFP+ Multi-Source Agreement (MSA). It has been designed to
meet the harshest external operating conditions including temperature, humidity and EMI
interference.
Formerica Optoelectronics Inc
.
5F-11, No.38, Taiyuan St.,Zhubei City,
Hsinchu County 30265, Taiwan
Ph: +886-3-5600286 Fax: +886-3-5600239
Version 01
1.0
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100Gb/s QSFP Transceiver
P
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:TGW-Q14BB-FCQ
Functional Description
The transceiver module receives 4 channels of 25Gb/s electrical data, which are processed by a 4-
channel Clock and Data Recovery (CDR) IC that reshapes and reduces the jitter of each electrical signal.
Subsequently, each of 4 EML laser driver IC's converts one of the 4 channels of electrical signals to an
optical signal that is transmitted from one of the 4 cooled EML lasers which are packaged in the
Transmitter Optical Sub-Assembly (TOSA). Each laser launches the optical signal in specific wavelength
specified in IEEE802.3ba 100GBASE-LR4 requirements. These 4-lane optical signals will be optically
multiplexed into a single fiber by a 4-to-1 optical WDM MUX. The optical output power of each channel
is maintained constant by an automatic power control (APC) circuit. The transmitter output can be turned
off by TX_DIS hardware signal and/or 2-wire serial interface.
The receiver receives 4-lane LAN WDM optical signals. The optical signals are de-multiplexed by a 1-to-
4 optical DEMUX and each of the resulting 4 channels of optical signals is fed into one of the 4 receivers
that are packaged into the Receiver Optical Sub-Assembly (ROSA). Each receiver converts the optical
signal to an electrical signal. The regenerated electrical signals are retimed and de-jittered and amplified
by the RX portion of the 4-channel CDR. The retimed 4-lane output electrical signals are compliant with
IEEE CAUI-4 interface requirements. In addition, each received optical signal is monitored by the DOM
section. The monitored value is reported through the 2-wire serial interface. If one or more received
optical signal is weaker than the threshold level, RX_LOS hardware alarm will be triggered.
A single +3.3V power supply is required to power up this product. Both power supply pins VccTx and
VccRx are internally connected and should be applied concurrently. As per MSA specifications the
offers 7 low speed hardware control pins (including the 2-wire serial interface): ModSelL, SCL, SDA,
ResetL, LPMode, ModPrsL and IntL.
Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2-wire
serial communication commands. The ModSelL allows the use of this product on a single 2-wire interface
bus – individual ModSelL lines must be used.
Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface
and enable the host to access the QSFP28 memory map.
The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on
the ResetL pin is held for longer than the minimum pulse length. During the execution of a reset the host
shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates
this by posting an IntL (Interrupt) signal with the Data_Not_Ready bit negated in the memory map. Note
that on power up (including hot insertion) the module should post this completion of reset interrupt
without requiring a reset.
Low Power Mode (LPMode) pin is used to set the maximum power consumption for the product in order
to protect hosts that are not capable of cooling higher power modules, should such modules be
accidentally inserted.
Formerica Optoelectronics Inc
.
5F-11, No.38, Taiyuan St.,Zhubei City,
Hsinchu County 30265, Taiwan
Ph: +886-3-5600286 Fax: +886-3-5600239
Version 01
1.0
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100Gb/s QSFP Transceiver
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Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is
normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path
to ground through a resistor on the host board and asserts the signal. ModPrsL then indicates its present
by setting ModPrsL to a “Low” state.
Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the
host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL
pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.
Transceiver Block Diagram
Pin Assignment and Pin Description
Formerica Optoelectronics Inc
.
5F-11, No.38, Taiyuan St.,Zhubei City,
Hsinchu County 30265, Taiwan
Ph: +886-3-5600286 Fax: +886-3-5600239
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1.0
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100Gb/s QSFP Transceiver
P
RODUCT
N
UMBER
:TGW-Q14BB-FCQ
Pin Definitions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LVTTL-I
LVTTL-O
LVTTL-O
CML-O
CML-O
CML-O
CML-O
CML-O
CML-O
CML-O
CML-O
LVCMOS-I/O
LVCMOS-I/O
LVTLL-I
LVTLL-I
CML-I
CML-I
CML-I
CML-I
Logic
Symbol
GND
Tx2n
Tx2p
GND
Tx4n
Tx4p
GND
ModSelL
ResetL
VccRx
SCL
SDA
GND
Rx3p
Rx3n
GND
Rx1p
Rx1n
GND
GND
Rx2n
Rx2p
GND
Rx4n
Rx4p
GND
ModPrsL
IntL
VccTx
Vcc1
LPMode
GND
Ground
Transmitter Inverted Data Input
Transmitter Non-Inverted Data output
Ground
Transmitter Inverted Data Input
Transmitter Non-Inverted Data output
Ground
Module Select
Module Reset
+3.3V Power Supply Receiver
2-Wire Serial Interface Clock
2-Wire Serial Interface Data
Ground
Receiver Non-Inverted Data Output
Receiver Inverted Data Output
Ground
Receiver Non-Inverted Data Output
Receiver Inverted Data Output
Ground
Ground
Receiver Inverted Data Output
Receiver Non-Inverted Data Output
Ground
Receiver Inverted Data Output
Receiver Non-Inverted Data Output
Ground
Module Present
Interrupt
+3.3 V Power Supply transmitter
+3.3 V Power Supply
Low Power Mode
Ground
1
2
2
1
1
1
1
1
1
2
1
1
Name/Description
Note
1
Formerica Optoelectronics Inc
.
5F-11, No.38, Taiyuan St.,Zhubei City,
Hsinchu County 30265, Taiwan
Ph: +886-3-5600286 Fax: +886-3-5600239
Version 01
1.0
5
Version 01
Page 5
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