TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
Rev. 2 — 24 April 2013
Product data sheet
1. General description
The TJA1022 is a dual LIN transceiver that provides the interface between a Local
Interconnect Network (LIN) master/slave protocol controller and the physical bus in a LIN
network. It is primarily intended for in-vehicle subnetworks using baud rates up to 20 kBd
and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602. The TJA1022 is
pin compatible with the TJA1020, TJA1021 and TJA1027 (see
Section 18).
The TJA1022
and TJA1027 are also software compatible.
The transmit data streams generated by the protocol controller are converted by the
TJA1022 into optimized bus signals shaped to minimize ElectroMagnetic Emissions
(EME). The LIN bus output pins are pulled HIGH via internal termination resistors. For a
master application, an external resistor in series with a diode should be connected
between pin V
BAT
and each of the LIN pins. The receivers detect receive data streams on
the LIN bus input pins and transfer them via pins RXD1 and RXD2 to the microcontroller.
Power consumption is very low when both transceivers are in Sleep mode. However, the
TJA1022 can still be woken up via pins LIN1/LIN2 and SLP1_N/SLP2_N.
2. Features and benefits
2.1 General
Two LIN transceivers in a single package
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602 compliant
Baud rate up to 20 kBd
Very low ElectroMagnetic Emissions (EME)
Very low current consumption in Sleep mode with remote LIN wake-up
Input levels compatible with 3.3 V and 5 V devices
Integrated termination resistors for LIN slave applications
Passive behavior in unpowered state
Operational during cranking pulse: full operation from 5 V upwards
Undervoltage detection
K-line compatible
Available in SO14 and HVSON14 packages
Leadless HVSON14 package (3.0 mm
4.5 mm) with improved Automated Optical
Inspection (AOI) capability
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
Pin-compatible with the TJA1020, TJA1021 and TJA1027 (see
Section 18)
Software-compatible with the TJA1027
NXP Semiconductors
TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
2.2 Protection
Very high ElectroMagnetic Immunity (EMI)
Very high ESD robustness:
8
kV according to IEC 61000-4-2 for pins LIN1, LIN2 and
V
BAT
Bus terminal and battery pin protected against transients in the automotive
environment (ISO 7637)
Bus terminal short-circuit proof to battery and ground
Thermally protected
Initial TXD dominant check when switching to Normal mode
TXD dominant time-out function
3. Quick reference data
Table 1.
V
BAT
I
BAT
Quick reference data
Conditions
limiting values
operating range
battery supply current
Min
0.3
5
Typ
-
-
7
7
1600
Max
+42
18
10
10
3200
Unit
V
V
A
A
A
battery supply voltage
Symbol Parameter
Sleep mode (both channels); bus recessive (both 2.5
channels); V
LINx
= V
BAT
; V
SLPx_N
= 0 V
Standby mode (both channels); bus recessive
(both channels); V
LINx
= V
BAT
; V
SLPx_N
= 0 V
Normal mode (both channels); bus recessive
(both channels); V
TXDx
= 5 V; V
LINx
= V
BAT
;
V
SLPx_N
= 5 V
2.5
300
V
LIN
V
ESD
T
vj
voltage on pin LIN
electrostatic discharge voltage
virtual junction temperature
pins LIN1 and LIN2; limiting value; with respect
to GND and V
BAT
on pins LIN1, LIN2 and V
BAT
; according to IEC
61000-4-2
42
8
40
-
-
-
+42
+8
+150
V
kV
C
4. Ordering information
Table 2.
Ordering information
Package
Name
TJA1022T
TJA1022TK
SO14
HVSON14
Description
plastic small outline package; 14 leads; body width 3.9 mm
plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3
4.5
0.85 mm
Version
SOT108-1
SOT1086-2
Type number
TJA1022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
2 of 26
NXP Semiconductors
TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
5. Block diagram
TJA1022
POWER-ON RESET AND
UNDERVOLTAGE DETECTION
RXD1
1
BUS
TIMER
13
SLP1_N
2
LIN1
10
V
BAT
TXD1
3
DOM
TIMER
RXD2
4
CONTROL
TEMPERATURE
PROTECTION
V
BAT
BUS
TIMER
SLP2_N
5
9
LIN2
TXD2
7
DOM
TIMER
8
GND
015aaa288
Fig 1.
Block diagram
TJA1022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
3 of 26
NXP Semiconductors
TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
6. Pinning information
6.1 Pinning
TJA1022T
RXD1
SLP1_N
TXD1
RXD2
SLP2_N
n.c.
TXD2
1
2
3
4
5
6
7
015aaa286
terminal 1
index area
14 n.c.
13 LIN1
12 n.c.
11 n.c.
10 V
BAT
9
8
LIN2
GND
RXD1
SLP1_N
TXD1
RXD2
SLP2_N
n.c.
TXD2
1
2
3
4
5
6
7
TJA1122TK
14 n.c.
13 LIN1
12 n.c.
11 n.c.
10 V
BAT
9
8
015aaa287
LIN2
GND
a. TJA1022T: SO14 package
Fig 2.
Pin configuration diagrams
b. TJA1022TK: HVSON14 package
6.2 Pin description
Table 3.
Symbol
RXD1
SLP1_N
TXD1
RXD2
SLP2_N
n.c.
TXD2
GND
LIN2
V
BAT
n.c.
n.c.
LIN1
n.c.
[1]
Pin description
Pin
1
2
3
4
5
6
7
8
[1]
9
10
11
12
13
14
Description
receive data output 1 (open-drain); active LOW after a wake-up event
sleep control input 1 (active LOW); resets wake-up request on RXD1
transmit data input 1
receive data output 2 (open-drain); active LOW after a wake-up event
sleep control input 2 (active LOW); resets wake-up request on RXD2
not connected
transmit data input 2
ground
LIN bus line 2 input/output
battery supply
not connected
not connected
LIN bus line 1 input/output
not connected
For enhanced thermal and electrical performance, the exposed center pad of the HVSON14 package
should be soldered to board ground (and not to any other voltage level).
TJA1022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
4 of 26
NXP Semiconductors
TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
7. Functional description
The TJA1022 is the interface between the LIN master/slave protocol controller and the
physical bus in a LIN network. According to the Open System Interconnect (OSI) model,
this is the LIN physical layer.
The LIN transceivers are optimized for, but not limited to, automotive applications with
excellent ElectroMagnetic Compatibility (EMC) performance.
7.1 LIN 2.x/SAE J2602 compliant
The TJA1022 is fully LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602 compliant. The
LIN physical layer is independent of higher OSI model layers (e.g. the LIN protocol).
Consequently, nodes containing a LIN 2.2A-compliant physical layer can be combined,
without restriction, with LIN physical layer nodes that comply with earlier revisions
(LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0, LIN 2.1 and LIN 2.2).
7.2 Operating modes
The transceivers are fully operational in Normal mode. A low-power Sleep mode is also
supported, as well as a Reset mode. Standby mode facilitates the transition between
Sleep and Normal modes.
The transceivers operate independently (except in Reset mode), so one transceiver can
be in Normal mode while the other is Sleep or Standby etc. Power consumption is at a
minimum when both transceivers are in Sleep mode.
7.2.1 Normal mode
In Normal mode, the TJA1022 can transmit and receive data via the LIN bus lines. The
transceivers operate independently, so one can be active while the other is off.
A transceiver will switch from Sleep or Standby mode to Normal mode if SLPx_N is held
HIGH for t
gotonorm
. If SLPx_N is held LOW for t
gotosleep
, the transceiver will switch from
Normal to Sleep mode.
The receivers detect data streams on the LIN bus lines (via pins LIN1 and LIN2) and
transfer the input via pins RXD1 and RXD2 to the microcontroller (see
Figure 6):
HIGH for
a recessive level and LOW for a dominant level on the bus. The receivers have
supply-voltage related thresholds with hysteresis and integrated filters to suppress bus
line noise.
Transmit data streams from the protocol controller are detected on the TXDx pins and are
converted by the transmitters into optimized bus signals shaped to minimize EME. The
LIN bus output pins are pulled HIGH via internal slave termination resistors. For a master
application, an external resistor in series with a diode should be connected between pin
V
BAT
and the appropriate LINx pin (see
Figure 6).
TJA1022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
5 of 26
模拟电子
