Dual Low Drop Voltage Regulator
TLE 4473 GV53
TLE 4473 GV52
Features
•
•
•
•
•
•
•
•
•
•
•
•
Output 1: 300 mA, 3.3 V (±3%) or 2.6 V (±3%)
Output 2: 180 mA, 5 V (±2%)
Low quiescent current consumption
Disable function separately for both outputs
Wide operation range: up to 42 V
Very low dropout voltage
2 independent reset circuits
Watchdog
Output protected against short circuit
Wide temperature range: -40
°C
to 150
°C
Overtemperature protection
Overload protection
Functional Description
The TLE 4473 is a monolithic integrated voltage regulator with two very low-drop
outputs, Q1 for loads up to 300 mA and Q2 providing a maximum of 180 mA. An input
voltage in the range of 5.6 V
≤
V
I
≤
45 V is transformed to
V
Q2
= 5.0 V (±2%) and
V
Q1
= 3.3 V
±3%
(TLE 4473 GV53) or
V
Q1
= 2.6 V
±3%
(TLE 4473 GV52). The device is
also available with dual 5 V output voltage, please refer to the TLE 4473 GV55 data
sheet. Two inhibit pins allow a flexible power management. Both outputs can
independently be enabled or disabled. Thus the current consumption of the application
can be reduced to a minimum. The quiescent current of the TLE 4473 with both outputs
disabled is < 1
µA.
The TLE 4473 is designed to supply microprocessor systems and
sensors under the severe conditions of automotive applications and is therefore
equipped with additional protection functions against overload, short circuit and
overtemperature.
The device operates in the wide junction temperature range of -40
°C
to 150
°C.
Type
TLE 4473 GV53
TLE 4473 GV52
Data Sheet
1
Package
PG-DSO-12
PG-DSO-12
Rev. 1.1, 2008-09-19
TLE 4473 GV53
TLE 4473 GV52
The low drop regulator features a reset with adjustable power on delay for each of the
outputs. In addition the output for the microcontroller supply comes up with a watchdog
in order to supervise a microcontroller.
V
Bat
7
I
TLE 4473 GV53 / TLE 4473 GV52
Q2 4
10
µF
e. g. µC I/O
or Sensor
Supply
4.7 k
Ω
Overtemperature
Shutdown
Bandgap
Reference
Current and
Saturation
Control,
Overcurrent
Protection
Reset
Generator
RO2 2
?1
D2 10
µC
9 INH2
Inhibit
100 nF
Q1 5
22 µF
or
10 µF
Current and
Saturation
Control,
Overcurrent
Protection
Ignition
8 INH1
Inhibit
Reset
Generator
RO1 3
µC Core
Supply
4.7 k
Ω
µC
Reset
Watchdog
WI 1
Watchdog
(from µC)
D1 11
100 nF
6, 12
GND
AEB03507.VSD
Figure 1
Block Diagram with Typical External Components
Data Sheet
2
Rev. 1.1, 2008-09-19
TLE 4473 GV53
TLE 4473 GV52
Reset and Watchdog Behaviour:
The reset output RO1 is in high-state if the voltage on the delay capacitor
C
D1
is greater
or equal
V
DL1
. The delay capacitor
C
D1
is charged with the current
I
DC1
for output voltages
greater than the reset threshold
V
RT1
. If the output voltage drops below
V
RT1
(“reset
condition”), the delay capacitor
C
D1
will be discharged rapidly. If
V
D1
reaches
V
DL1
, the
reset output RO1 is set to low.
At power-on, the charging process of
C
D1
starts from 0 V, which leads to the equation
C
D1
×
V
DU1
t
D, on
= ----------------------------
-
I
DC1
for the power-on reset delay time.
(1)
When the voltage at the delay capacitor has reached
V
DU1
and RO1 was set to high, the
watchdog circuit is enabled and discharges
C
D1
with the constant current
I
DD1
.
If there is no rising edge observed at the watchdog input,
C
D1
will be discharged down to
V
DL1
, where the reset output RO1 will be set to low and
C
D1
will be charged again with
the current
I
DC1
until
V
D1
reaches
V
DU1
and reset will be set high again.
If a watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period,
C
D1
is charged again and the reset output stays high. After
V
D1
has reached
V
DU1
,
the periodical cycle starts again.
The watchdog timing is shown in
Figure 2.
The maximum duration between two
watchdog pulses corresponds to the minimum watchdog trigger time T
WI,tr
. Higher
capacitances on pin D1 result in larger watchdog trigger time:
T
WI,tr
=
0.42 ms/nF
×
C
D1
(2)
max
If the output voltage Q2 decreases below
V
RT2
, the external capacitor
C
D2
is discharged.
When the voltage at this capacitor drops below
V
DL2
, a reset signal is generated at pin
11 (RO2), i.e. the reset output is set to low-level. If the output voltage rises above the
reset threshold,
C
D2
will be charged with the constant current
I
DC2
. After the power-on-
reset time, the voltage at the capacitor reaches
V
DU2
and the reset output will be set to
high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of
C
D2
using
Equation (1)
analogous for Q2.
Data Sheet
3
Rev. 1.1, 2008-09-19
TLE 4473 GV53
TLE 4473 GV52
V
W
Ι
V
Ι
t
V
Q
T
WD, p
t
V
D1
V
DU1
V
DL1
V
WO
T
WI, tr
t
t
WD, L
t
T
WI, tr
=
(
V
DU1
-
V
DL1
)
Ι
DD1
C
D1
;
T
WD, p
=
(
V
DU1
-
V
DL1
) (
Ι
DC1
+
Ι
DD1
)
Ι
DC1
x
Ι
DD1
C
D1
;
t
WD, L
=
(
V
DU1
-
V
DL1
)
t
Ι
DC1
C
D1
AED03099_4473gv53
Figure 2
Watchdog Timing Schedule
Data Sheet
4
Rev. 1.1, 2008-09-19
TLE 4473 GV53
TLE 4473 GV52
P-DSO-12-6
WI
RO2
RO1
Q2
Q1
N.C.
1
2
3
4
5
6
12
11
10
9
8
7
GND
D1
D2
INH2
INH1
I
AEP03318_4473gv53.VSD
Pin 6 and heat slug should be connected to GND
Figure 3
Table 1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Heatsink
Data Sheet
Pin Configuration TLE 4473 GV53, TLE 4473 GV52
(top view)
Pin Definitions and Functions (TLE 4473 GV53, TLE 4473 GV52)
Symbol Function
WI
RO2
RO1
Q2
Q1
N.C.
I
INH1
INH2
D2
D1
GND
N. C.
Watchdog input;
input for watchdog pulses, positive edge
triggered
Reset output for Q2;
open collector output
Reset and watchdog output for Q1;
open collector output
Output voltage 2 (5 V);
block to GND with a capacitor
C
Q2
≥
22
µF,
ESR < 5
Ω
at 10 kHz or
C
Q2
≥
10
µF,
ESR < 4
Ω
at 10 kHz
Output voltage 1 (3.3 V/2.6 V);
block to GND with a capacitor
C
Q1
≥
10
µF,
ESR < 5
Ω
at 10 kHz
Not connected;
connect to GND
Input voltage;
block to GND directly at the IC with a ceramic
capacitor.
Inhibit input 1;
low level at INH2 and INH1 disables Q2 and Q1
Inhibit input 2;
low level disables Q2
Reset Delay 2;
connect a capacitor to set reset delay for Q2
Reset Delay 1;
connect a capacitor to GND to set reset delay and
watchdog timing for Q1
Ground
Not connected;
connect to GND
5
Rev. 1.1, 2008-09-19
