TLP104
TOSHIBA PHOTOCOUPLER IRED & PHOTO-IC
TLP104
IPM (Intelligent Power Module)
Industrial Inverter
Operate at high ambient temperatures up to 125°C
The Toshiba TLP104 consists of an infrared emitting diodes and integrated
high gain, high-speed photodetectors. The TLP104 is housed in the SO6
package. The output stage is an open collector type.
The photodetector has an internal Faraday shield that provides a
guaranteed common-mode transient immunity of ±15 kV/μs. TLP104
guarantees minimum and maximum of propagation delay time, switching
speed dispersion, and high common mode transient immunity. Therefore
TLP104 is suitable for isolation interface between IPM (Intelligent Power
Module) in motor control application.
Inverter logic type (Open collector output)
Package type:
SO6
-40 to 125°C
JEDEC
―
JEITA
―
TOSHIBA
11-4L1
Weight: 0.08 g(typ.)
Unit: mm
Guaranteed performance over temperature:
Power supply voltage: -0.5 to 30 V
Threshold Input Current:
I
FHL
= 5.0 mA (max)
t
pHL
= 400ns (max)
t
pLH
= 550ns (max)
Propagation delay time (t
pHL
/t
pLH
):
Switching Time Dispersion(|t
pHL
-t
pLH
|):
Common mode transient immunity
Isolation voltage
:
:
400ns (max)
±15kV/μs (min)
3750Vrms (min)
Pin Configuration (Top View)
1
V
CC
6
5
UL-recognized : UL 1577, File No.E67349
cUL-recognized : CSA Component Acceptance Service No.5A
File No.E67349
3
SHIELD
GND
4
1:ANODE
3:CATHODE
4:GND
5:V
O
(Output)
6:V
CC
VDE-approved : EN 60747-5-5, EN 62368-1
(Note 1)
CQC-approved : GB4943.1, GB8898 Thailand Factory
Schematic
IF
1+
I
CC
IO
6
5
V
CC
V
O
Note 1 : When a VDE approved type is needed,
please designate the
Option(V4).
3-
SHIELD
GND
Truth Table
Input
H
L
LED
ON
OFF
Output
L
H
Construction Mechanical Ratings
Creepage distance
Clearance distance
Insulation thickness
5.0 mm (min)
5.0 mm (min)
0.4 mm (min)
4
Start of commercial production
© 2019
Toshiba Electronic Devices & Storage Corporation
2009-10
1
2019-05-27
TLP104
Absolute Maximum Ratings
(Ta = 25°C)
Characteristic
Forward Current
Forward Current Derating
Pulse Forward Current
LED
Pulse Forward Current Derating (Ta
≥
110°C)
Reverse Voltage
Input Power Dissipation
Input power Dissipation Derating (Ta
≥
110°C)
Output Current
Detector
Output Voltage
Supply Voltage
Output Power Dissipation
Output Power Dissipation Derating (Ta
≥
110°C)
Operating Temperature Range
Storage Temperature Range
Lead Soldering Temperature (10 s)
Isolation Voltage (AC,60 s, R.H.
≤
60 %,Ta=25°C)
(Note 2)
(Ta
≤
125°C)
(Ta
≥
110°C)
(Note 1)
Symbol
IF
ΔI
F /°C
IFP
ΔI
FP /°C
VR
P
D
ΔP
D
/°C
IO
VO
VCC
PO
ΔP
O /°C
Topr
Tstg
Tsol
BVs
Rating
25
-0.67
50
-1.34
5
40
-1.0
8
-0.5 to 30
-0.5 to 30
80
-2.0
-40 to 125
-55 to 125
260
3750
Unit
mA
mA/°C
mA
mA/°C
V
mW
mW/°C
mA
V
V
mW
mW/°C
°C
°C
°C
Vrms
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc.).
Note 1: Pulse width
≤
10
μs,
duty=10 %.
Note 2: This device is regarded as a two terminal device: pins 1 and 3 are shorted together, as are pins 4, 5 and 6.
Recommended Operating Conditions
Characteristic
Input Current , High Level
Input Voltage , Low Level
Supply Voltage*
Operating Temperature
Symbol
IFHL
VFLH
VCC
Topr
Min
7.5
0
4.5
-40
Typ.
-
-
-
-
Max
15
0.8
30
125
Unit
mA
V
V
°C
* This item denotes operating range, not meaning of recommended operating conditions.
Note: Recommended operating conditions are given as a design guideline to obtain expected performance of the
device. Additionally, each item is an independent guideline respectively. In developing designs using this
product, please confirm specified characteristics shown in this document.
© 2019
Toshiba Electronic Devices & Storage Corporation
2
2019-05-27
TLP104
Electrical Characteristics
(Unless otherwise specified, Ta
= −40
to 125°C, VCC =4.5 to 30V)
Characteristic
Forward voltage
LED
Forward voltage
temperature coefficient
Reverse current
Capacitance between
terminals
High level output current
Detector
Low level output voltage
Low level supply current
High level supply current
Output current
Input current logic LOW output
Input voltage logic HIGH output
Symbol
V
F
ΔV
F
/
ΔTa
I
R
C
T
I
OH
V
OL
I
CCL
I
CCH
I
O
I
FHL
V
FLH
Test
Circuit
―
―
―
―
1
2
3
4
―
―
―
Test Condition
I
F
= 10 mA, Ta = 25 °C
I
F
= 10 mA
V
R
= 5 V, Ta = 25 °C
V = 0 V, f = 1 MHz
V
F
= 0.8 V, V
O
< V
CC
I
F
= 10 mA, I
O
= 2.4 mA
I
F
= 10 mA
I
F
= 0 mA
I
F
= 10 mA, V
O
= 0.6 V
I
O
= 0.75mA, V
O
< 0.8 V
I
O
= 0.75mA, V
O
> 2.0 V
Min
1.45
―
―
―
―
―
―
―
4.0
―
0.8
Typ.
1.61
-1.8
―
60
―
0.2
―
―
―
1.0
―
Max
1.85
―
10
―
50
0.6
1.3
1.3
Unit
V
mV /°C
μA
pF
μA
V
mA
mA
mA
mA
V
―
5
―
*
All typical values are at Ta = 25° C, VCC = 5 V unless otherwise specified
Isolation Characteristics
(Ta = 25°C)
Characteristic
Capacitance input to output
Isolation resistance
Isolation voltage
Symbol
C
S
R
S
BV
S
Test Conditions
V
S
= 0 V, f = 1 MHz
R.H.
≤
60 %, V
S
= 500 V
AC,60 s
Min
―
1×10
12
3750
Typ.
0.8
10
14
―
Max
―
―
―
Unit
pF
Ω
V
rms
© 2019
Toshiba Electronic Devices & Storage Corporation
3
2019-05-27
TLP104
Switching Characteristics
(
Unless otherwise specified, Ta
= −40
to 125°C, V
CC
=15V)
Characteristic
Propagation delay time (H→L)
Symbol
t
pHL
Test
Circuit
Test Condition
CL=100 pF
CL=10 pF
CL=100 pF
5
|t
pHL−
t
pLH
|
I
F
= 10 mA,
R
L
= 20 kΩ
(Note 1)
CL=10 pF
Min
30
―
150
―
―
C
L
= 100 pF
t
pLH−
t
pHL
CM
H
6
CM
L
V
CM
= 1500 V
p−p
, I
F
= 0 mA
R
L
= 20 kΩ, Ta = 25 °C
V
CM
= 1500 V
p−p,
I
F
= 10 mA
R
L
= 20 kΩ, Ta = 25 °C
-50
15
−15
―
―
―
450
―
―
kV/μs
kV/μs
Typ.
150
90
350
100
―
Max
400
―
550
―
400
ns
Unit
Propagation delay time (L→H)
Switching Time Dispersion
between ON and OFF
Propagation Delay Skew (Note 2)
Common mode transient immunity
at high output level
Common mode transient Immunity
at low output level
*All typical values are at Ta = 25
°C
t
pLH
Note :
A ceramic capacitor (0.1
μF)
should be connected from pin 6 (
VCC
) to pin 4 (GND) to stabilize the operation
of the high gain linear amplifier. Failure to provide the bypass may impair the switching property.
The total lead length between capacitor and coupler should not exceed 1 cm.
Note 1: f = 10kHz, duty=10%, input current tr = tf = 5 ns
Note 2: Propagation delay skew is defined as the propagation delay time of the largest or smallest t
pLH
minus
the largest or smallest t
pHL
of multiple samples. Evaluations of these samples are conducted under identical
test conditions (supply voltage, input current, temperature, etc.).
TEST CIRCUIT 1: IOH
TEST CIRCUIT 2: VOL
0.1μF
VF
IOH
0.1μF
VCC
IF
SHIELD
VOL IO
↑
V
VCC
A
SHIELD
VO
TEST CIRCUIT 3: ICCL
ICCL
A
TEST CIRCUIT 4: ICCH
ICCH
A
IF
SHIELD
0.1
μF
VCC
SHIELD
0.1
μF
VCC
© 2019
Toshiba Electronic Devices & Storage Corporation
4
2019-05-27
TLP104
Test Circuit 5: t
pHL
, t
pLH
, |t
pHL
-t
pLH
|
IF=10mA(P.G)
(f=10kHz , duty=10%, tr=tf=5ns)
P.G.
0.1μF
IF Monitor
SHIELD
RIN=100Ω
C
L
R
L
=20kΩ
VO
VO
VCC
VOL
VTHHL=1.5 V
VTHLH=2.0 V
tpHL
tpLH
IF
50%
15pF*
*: probe and stray capacitance.
P.G.: Pulse generator
Test Circuit 6: CM
H
, CM
L
90%
1500 V
SW
A
B
→
IF
R
L
=20kΩ
0.1
μF
VO
VCC
SHIELD
VCM
10%
tr
・SW
B : IF = 0 mA
VO
・SW
A : IF = 10 mA
11V
tf
CMH
1.0 V
CML
＋
VCM
－
CM
H
＝
1200(V)
t
r(μs)
CM
L
＝
-
1200(V)
t
f(μs)
© 2019
Toshiba Electronic Devices & Storage Corporation
5
2019-05-27
