Preliminary Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Features
I
Applications
I
I
I
I
I
Multiplexes three STS-1 signals into a SONET
STS-3 signal.
Multiplexes three AU-3 signals into an SDH STM-1
(AU-4) signal via a TUG-3 construction.
Demultiplexes three STS-1 signals from a SONET
STS-3 signal.
Demultiplexes three AU-3 signals from an SDH
STM-1 (AU-4) signal via a TUG-3 deconstruction.
High-speed microprocessor interface configurable
to operate with most commercial microprocessors.
Detects STS-3/STM-1 (AU-4) loss-of-signal (LOS)
conditions.
Detects STS-3/STM-1 (AU-4) out-of-frame and
loss-of-frame (OOF/LOF) conditions.
Provides an 8-bit bus interface at the STS-1/AU-3
rate.
Provides a bit serial, nibble-wide, or byte-wide
interface at STS-3/STM-1 (AU-4) rate.
Provides STS-3/STM-1 (AU-4) selectable scram-
bler/descrambler functions and B1/B2/B3 genera-
tion/detection.
Accepts bit rate, nibble rate, or byte rate high-
speed clocks (155.52 MHz, 38.88 MHz, or
19.44 MHz, respectively).
STS-3/STM-1 (AU-4) internal clock and data
recovery. Meets type B jitter tolerance of ITU-T
G.958. Accommodates 0.5 UI jitter up to 20 MHz.
155.52 MHz input reference clock for on-chip PLL.
Has on-chip PLL for clock synthesis, requiring only
one external resistor. No output clock drift in
absence of data transitions once lock is acquired.
STS-1 termination mode.
–40 °C to +85 °C temperature range.
208-pin, shrink quad flat pack (SQFP) package.
Complies with GR-253-CORE (12/95), G.707
(3/96), G.783(1/94).
SONET/SDH line termination equipment.
SDH path origination and termination equipment.
SONET/SDH add/drop multiplexers.
SONET/SDH cross connects.
SONET/SDH test equipment.
I
I
I
Description
The TMUX03155 STS-3/STM-1 (AU-4) multiplexer
device provides three modes of operation: STS-3,
STM-1 (AU-4), and STS-1 modes. In STS-3 mode,
the TMUX03155 device provides all of the functions
necessary to multiplex and demultiplex up to three
STS-1 signals to/from a SONET STS-3 signal. In
AU-4 mode, the TMUX03155 provides the functional-
ity to multiplex and demultiplex up to three AU-3 sig-
nals to/from an STM-1 (AU-4) signal. In STS-1 mode,
the high-speed side of the TMUX03155 operates at
51.84 MHz and can be used for STS-1 termination
and for accessing transport overhead in the SONET
frame. On the STS-3/STM-1 (AU-4) side, the device
can be configured for either a 1-bit serial data inter-
face, a 4-bit parallel (nibble-wide) data interface, or
an 8-bit parallel (byte-wide) data interface. This
allows the device to drive an OC3 optical signal
directly or to allow for modular growth in terminal or
add/drop applications. On the STS-1/AU-3 side, the
TMUX03155 device provides a bus mode that can
communicate with up to three STS-1/AU-3 devices at
19.44 Mbits/s. The TMUX03155 is designed to inter-
face with the Agere Systems Inc. TMPR28051
device, or equivalent, providing complete mapping/
unmapping from/to an STS-3/STM-1 (AU-4) signal
for up to 84 DS1 or 63 E1 signals.
I
I
I
I
I
I
I
I
I
I
I
I
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Preliminary Data Sheet
April 2001
Table of Contents
Contents
Page
Features ................................................................................................................................................................... 1
Applications .............................................................................................................................................................. 1
Description ................................................................................................................................................................ 1
Nomenclature Assumptions ...................................................................................................................................... 7
Block Diagram ..........................................................................................................................................................7
Pin Information ......................................................................................................................................................... 9
Summary of I/O Pins .........................................................................................................................................15
Mode Control Signals (See Register Description on page 54.) ..............................................................................16
STS-1 Mode ...........................................................................................................................................................16
Transmit Direction Overview ..................................................................................................................................17
STS-1/AU-3 Bus Mode Input Retiming ..............................................................................................................17
Input Select Control ...........................................................................................................................................17
STS-1/AU-3 Inputs ............................................................................................................................................17
Out-of-Frame (OOF) and Loss-of-Frame (LOF) Monitoring ..............................................................................18
Descramble Enable/Disable ..............................................................................................................................18
Monitor B1 and B2 Errors ..................................................................................................................................19
H4 Multiframe and Pointer Monitor (AU-4 Mode Only) ......................................................................................19
STS-3 Generate ................................................................................................................................................20
Transport Overhead Access Channel (TOAC) Insert ........................................................................................23
STS-3/STM-1 (AU-4) Scramble Enable ............................................................................................................23
STS-3/STM-1 (AU-4) B1, B2, and B3 BIP Generation ......................................................................................23
STS-3/STM-1 (AU-4) Loopback Control ............................................................................................................23
STS-3/STM-1 (AU-4) Output Interface ..............................................................................................................23
Receive Direction Overview ...................................................................................................................................23
Input Retime ......................................................................................................................................................24
Clock and Data Recovery ..................................................................................................................................24
STS-3/STM-1 (AU-4) Framing ...........................................................................................................................24
Loss of Signal ....................................................................................................................................................24
Loopback Select Logic ......................................................................................................................................25
RSTS-3/STM-1 (AU-4) Frame Synchronous Descrambling (SONET/SDH) .....................................................25
TOAC Drop ........................................................................................................................................................25
B1, B2, and B3 Checking ..................................................................................................................................25
Monitoring Functions .........................................................................................................................................25
Pointer Interpretation .........................................................................................................................................25
Data Demultiplex and Conversion (AU-4 Mode Only) .......................................................................................26
STS-1/AU-3 Output Byte Control ......................................................................................................................26
B1 and B2 Generate ..........................................................................................................................................26
STS-1/AU-3 Output Scramble ...........................................................................................................................27
Output Selection Logic ......................................................................................................................................27
Output Data Formatter ......................................................................................................................................27
Maintenance Functions ..........................................................................................................................................27
Maintenance Functions Disabled During Failure Conditions .............................................................................28
Common Maintenance and Control Functions ..................................................................................................28
Transmit Functions ............................................................................................................................................30
Receive Functions .............................................................................................................................................38
Typical Uses ...........................................................................................................................................................45
Section and Line Termination Multiplex ............................................................................................................45
Add/Drop Multiplex ............................................................................................................................................46
Digital Cross Connect ........................................................................................................................................46
Microprocessor Interface ........................................................................................................................................47
Overview ...........................................................................................................................................................47
2
Agere Systems Inc.
Preliminary Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Table of Contents
(continued)
Contents
Page
Microprocessor Configuration Modes ................................................................................................................47
Microprocessor Interface Pinout Descriptions ...................................................................................................47
Microprocessor Interface Register Architecture ................................................................................................49
Register Description ..........................................................................................................................................54
I/O Timing ........................................................................................................................................................101
Absolute Maximum Ratings ..................................................................................................................................106
Handling Precautions ...........................................................................................................................................106
Operating Conditions ............................................................................................................................................107
Electrical Characteristics ......................................................................................................................................108
Timing Characteristics ..........................................................................................................................................110
Operational Timing ..........................................................................................................................................110
Outline Diagram ....................................................................................................................................................117
208-Pin SQFP .................................................................................................................................................117
Ordering Information .............................................................................................................................................118
DS01-194PDH Replaces DS00-213TIC to Incorporate the Following Updates ...................................................118
Agere Systems Inc.
3
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Preliminary Data Sheet
April 2001
List of Figures
Contents
Page
Figure 1. TMUX03155 Block Diagram ................................................................................................................... 8
Figure 2. Pinout of 208 SQFP Device ................................................................................................................... 9
Figure 3. SFEBE Location ................................................................................................................................... 33
Figure 4. Line Termination Multiplex ................................................................................................................... 45
Figure 5. Add/Drop Multiplex ............................................................................................................................... 46
Figure 6. Digital Cross Connect ........................................................................................................................... 46
Figure 7. MODE 1—Read Cycle Timing (MPMODE = 0, MPMUX = 0) ............................................................ 102
Figure 8. MODE 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0) ............................................................. 102
Figure 9. MODE 2—Read Cycle Timing (MPMODE = 0, MPMUX = 1) ............................................................ 103
Figure 10. MODE 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1) ........................................................... 103
Figure 11. MODE 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0) .......................................................... 104
Figure 12. MODE 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0) ........................................................... 104
Figure 13. MODE 4—Read Cycle Timing (MPMODE = 1, MPMUX = 1) .......................................................... 105
Figure 14. MODE 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1) ........................................................... 105
Figure 15. Single-Ended Input Specification ..................................................................................................... 108
Figure 16. THSJ0J1V1I Signal Structure Definition ........................................................................................... 112
Figure 17. Interface Data Timing ....................................................................................................................... 115
Figure 18. Bus Interface Signals ....................................................................................................................... 116
4
Agere Systems Inc.
Preliminary Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
List of Tables
Contents
Page
Table 1. Pin Descriptions for the 208-Pin SQFP Package .................................................................................. 10
Table 2. Input/Output Summary .......................................................................................................................... 15
Table 3. Transmit Mode Control Signals ............................................................................................................. 16
Table 4. Receive Mode Control ........................................................................................................................... 16
Table 5. Input Select Control ............................................................................................................................... 17
Table 6. Expected STS-1/AU-3 Input Frame Format .......................................................................................... 18
Table 7. STS-3 Output Overhead Format ........................................................................................................... 20
Table 8. STM-1 (AU-4) Output Overhead Format ............................................................................................... 21
Table 9. STS-1/AU-3 Format and Overhead Control Summary .......................................................................... 26
Table 10. STS-1/AU-3 Output Select Control ...................................................................................................... 27
Table 11. Monitors Disabled During Failure Conditions ...................................................................................... 28
Table 12. SFEBE Values ..................................................................................................................................... 33
Table 13. G1 Byte—AU-4 Mode Only ................................................................................................................. 34
Table 14. PFEBE Values ..................................................................................................................................... 34
Table 15. Value Offset Load Values .................................................................................................................... 36
Table 16. Transport Overhead Byte Access—Transmit Direction ....................................................................... 36
Table 17. TTOAC Control Bits ............................................................................................................................. 37
Table 18. STS-1/AU-3 Overhead Control ............................................................................................................ 42
Table 19. Transport Overhead Byte Access—Receive Direction ........................................................................ 44
Table 20. Microprocessor Configuration Modes .................................................................................................. 47
Table 21. MODE [1—4] Microprocessor Pin Definitions ...................................................................................... 47
Table 22. Device-Level Register Map ................................................................................................................. 49
Table 23. Page 0—J1 Byte Insert and Monitor .................................................................................................... 51
Table 24. Page 1—Error Counters ...................................................................................................................... 52
Table 25. Page 2—BER Algorithm Parameters .................................................................................................. 53
Table 26. Register 0 (RO) ................................................................................................................................... 54
Table 27. Registers 1—3 (RO) ............................................................................................................................ 54
Table 28. Registers 4, 5: One-Shot Register 0
→
1 (R/W) .................................................................................. 54
Table 29. Register 6: Scratch Register (R/W) ..................................................................................................... 55
Table 30. Registers 7—15: Delta/Event (COR-RO) ............................................................................................ 55
Table 31. Registers 16—24: Mask Bits (R/W) ..................................................................................................... 60
Table 32. Registers 25—51: State Bits (RO) ....................................................................................................... 62
Table 33. Register 52: Mode Control (R/W) ........................................................................................................ 64
Table 34. Register 53: Low-Speed Transmit Common Signals (R/W) ................................................................ 65
Table 35. Register 54—59: Transmit Low-Speed Port Input Control (R/W) ........................................................ 66
Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W) ...................................................... 67
Table 37. Register 62: Transmit High-Speed Control Signals (R/W) .................................................................. 68
Table 38. Register 62, and Page 0, Registers 128—191: Transmit High-Speed J1 Insert (R/W) ....................... 69
Table 39. Register 62, 69: Transmit High-Speed Control Signals (R/W) ............................................................ 69
Table 40. Register 62, 66: Transmit High-Speed Control Signals (R/W) ............................................................ 69
Table 41. Registers 63—65: Trace/Growth Bytes (R/W) ..................................................................................... 69
Table 42. Register 66: Transmit F1 Data Byte (R/W) .......................................................................................... 70
Table 43. Registers 67 and 68: K1 and K2 Insert Bytes (R/W) ........................................................................... 70
Table 44. Register 69: Transmit Sync Status Byte (R/W) ................................................................................... 70
Table 45. Register 70: Path Signal Trace Byte (R/W) ......................................................................................... 70
Table 46. Register 71: Path User Channel Byte (R/W) ....................................................................................... 70
Table 47. Register 72: Path Growth Byte (R/W) .................................................................................................. 70
Table 48. Register 73: Tandem Connection Byte (R/W) ..................................................................................... 71
Table 49. Register 74: Transmit High-Speed Line RDI Insertion Inhibit Bits (R/W) ............................................ 71
Table 50. Register 75: Transmit High-Speed Path RDI Insertion Inhibit Bits (R/W) ............................................ 71
Table 51. Register 76: Transmit High-Speed Error Insert Control Parameters (R/W) ......................................... 72
Agere Systems Inc.
5
嵌入式系统
