Vectron International's TRU-050 module is a user-configured, phase-locked loop (PLL) solution designed to simplify a wide variety of clock recovery and data retiming,
frequency translation and clock smoothing applications. The device features a phase-lock loop ASIC with a quartz stabilized VCXO for superior stability and jitter performance.
This highly integrated module provides unsurpassed performance, reliability and quality. The proprietary ASIC device includes a refined Phase Detector, a Loop Filter Op-Amp,
a Loss of Signal Alarm with Clock Return to Nominal feature, a VCXO circuit, and an optional 2n divided output.
The ASIC and quartz resonator are housed in a hermetic 16-pin DIL ceramic package with optional thru-hole or surface mount leads. The VCXO frequency (OUT1) and
division factor (OUT2) are factory set in accordance with customer specifications. PLL response is optimized for each application by the selection of three external passive
components. Software is available from Vectron to aid in loop filter component selection and loop response modeling.
is a user-configured phase-locked loop (PLL) integrated circuit. It includes a voltage controlled crystal oscillator (VCXO), an operational amplifier, a phase
detector, and additional integrated functions for use in digital synchronization applications. These applications include timing recovery and data pulse restoration for data
signals, clock frequency translation and smoothing, synchronous distributed clock networks, and clock frequency synthesis.
What is the output of the
phase detector?
The TRU-050 phase detector output
is a DC signal, under locked
conditions, and is nominally 2.5
Volts. The phase error (which is
typically a pulse for digital phase
detectors) is converted to a DC
level, making it easy to design
the loop filter.
TRU-050 Elements
Figure 4.
How long does the
TRU-050 take to detect
a loss of signal?
If there are no transitions on
DATAIN for a period of 256 clock
cycles, LOS is set to a logic 1.
LOS is reset to logic 0 as soon as
there are DATAIN transitions.
Phase Dete c t o r
The phase detector is designed to accept an NRZ data stream at DATAIN (Pin 7- refer to figure 5), but may be used
for clock signals and other data types. The input buffers are designed to switch at a TTL switching threshold of 1.4 V.
The phase detector’s inputs are:
• DATAIN (Pin 7) - the input clock or NRZ data signal
• CLKIN (Pin 9) - the clock signal feedback from the VCXO output OUT1 or OUT2
And the outputs are:
• RCLK (Pin 11) - the regenerated clock signal
• RDATA (Pin 12) - the retimed data signal
• PHO (Pin 6) - the phase detector output
• LOS (Pin 10) - a loss of signal detector
The phase relationship between the regenerated clock signal, RCLK (Pin 11), and the regenerated data signal,
to align the falling edge of the RCLK signal with the center of each RDATA pulse.
For applications where the input clock or data signal, DATAIN, is very low in frequency (<200kHz), clock
information may pass through the phase detector because of its finite low pass characteristic. In applications
such as this, an additional pole may be necessary in the loop filter to attenuate these AC components prior to
the VCXO input. Please contact Vectron’s Applications Engineering staff for further detail.
How is it
manufactured?
The TRU-050 is
assembled in
Figure 6.
“state of the art”
class 100 and class
10,000 clean
rooms using leading
edge, high volume
automation equip-
ment and advanced
ASIC technology.
Figure 7.
Figure 8.
Phase Detector Gain Calculation
The schematic diagram (figure 7) shows a simplified representation of the phase detector's basic error generation function. The actual circuit is more complex and includes
circuitry to reduce the
TRU-050's
dependence on input data duty-cycle. In general, the
TRU-050
is insensitive to duty cycle and duty cycle changes. This circuit provides a
output (V D) DC level which is proportional to the relative phase of DATAIN (Pin 7) and CLKIN (Pin 9). A plot of the output (VD) versus relative phase is shown in figure
8. The slope of the output (VD ) versus relative phase (0 e) is 5V/2π.
The phase detector block also includes an output gain stage which should be considered when calculating the gain of the complete phase detector block. This gain stage
has a gain of 2/3, and converts the differential signal to a single-ended DC output.
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MSP430子程序（液晶控制器子程序） //------------------------------------------------------------ // Control SED1335 // TIme 2003.01.15 // Copyright 重庆东电 // FuncTIon show //----------------------------------------...[详细]
FPGA/CPLD
