The TS64MSD64V4F3 is a 64M x 64bits Double Data Rate
SDRAM high-density for DDR400. The TS64MSD64V4F3
consists of 16pcs CMOS 32Mx8 bits Double Data Rate
SDRAMs in 60 Ball SOC BGA packages and a 2048 bits
serial EEPROM on a 200-pin printed circuit board. The
TS64MSD64V4F3 is a Dual In-Line Memory Module and is
intended for mounting into 200-pin edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory
system applications.
200PIN DDR400 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
Placement
B
F D
A
C
G
H
I
J
PCB: 09-1710
E
K
Features
•
•
•
•
•
•
•
•
•
•
•
Power supply: VDD= VDDQ: 2.6V ± 0.1V,
Max clock Freq: 200MHZ.
Double-data-rate architecture; two data transfers per
clock cycle
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CLK transition
Commands entered on each positive CLK edge
Auto and Self Refresh.
Data I/O transactions on both edge of data strobe.
Serial Presence Detect (SPD) with serial EEPROM
SSTL-2 compatible inputs and outputs.
MRS cycle with address key programs.
CAS Latency (Access from column address) : 3
Burst Length (2,4,8)
Data Sequence (Sequential & Interleave)
Transcend Information Inc.
1
TS64MSD64V4F3
Dimensions
Side
A
B
C
D
E
F
G
H
I
J
K
Millimeters
67.60±0.20
47.40
11.40
4.20
2.15
1.80
2.55
4.00
20.00
31.75±0.20
1.00±0.10
Inches
2.661±0.008
1.866
0.449
0.165
0.085
0.071
0.100
0.157
0.787
1.250±0.008
0.039±0.004
200PIN DDR400 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
Pin Identification
Symbol
A0~A12, BA0, BA1
DQ0~DQ63
DQS0~DQS7
CK0~CK2
/CK0~/CK2
CKE0, CKE1
/CS0, /CS1
/RAS
/CAS
/WE
DM0~DM7
VDD
VREF
VDDSPD
Clock Enable Input.
Chip Select Input.
Row Address Strobe
Column Address Strobe
Write Enable
Data-in Mask
+2.5 Voltage power supply
Power Supply for Reference
+2.5 Voltage Serial EEPROM
Power Supply
SA0~SA2
SCL
SDA
VSS
NC
Address in EEPROM
Serial PD Clock
Serial PD Add/Data input/output
Ground
No Connection
Function
Address input
Data Input / Output.
Data strobe input/output
Clock Input.
(Refer Placement)
Transcend Information Inc.
2
TS64MSD64V4F3
Pinouts:
Pin
Pin
Pin
Pin
No
Name
No
Name
01
VREF
69
VDD
03
VSS
71
*CB0
05
DQ0
73
*CB1
07
DQ1
75
VSS
09
VDD
77
*DQS8
11
DQS0
79
*CB2
13
DQ2
81
VDD
15
VSS
83
*CB3
17
DQ3
85
DU
19
DQ8
87
VSS
21
VDD
89
*CK2
23
DQ9
91
*/CK2
25
DQS1
93
VDD
27
VSS
95
*CKE1
29
DQ10
97
*A13
31
DQ11
99
*A12
33
VDD
101
A9
35
CK0
103
VSS
37
/CK0
105
A7
39
VSS
107
A5
41
DQ16
109
A3
43
DQ17
111
A1
45
VDD
113
VDD
47
DQS2
115
A10
49
DQ18
117
BA0
51
VSS
119
/WE
53
DQ19
121
/CS0
55
DQ24
123
DU
57
VDD
125
VSS
59
DQ25
127
DQ32
61
DQS3
129
DQ33
63
VSS
131
VDD
65
DQ26
133
DQS4
67
DQ27
135
DQ34
* Please refer Block Diagram
Pin
No
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Pin
Name
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
D56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDD
Pin
No
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
200PIN DDR400 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
Pin
Name
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
Pin
No
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
Pin
Name
VDD
*CB4
*CB5
VSS
*DM8
*CB6
VDD
*CB7
DU
VSS
VSS
VDD
VDD
CKE0
DU
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
*/CS1
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
Pin
No
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Pin
Name
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
Transcend Information Inc.
3
TS64MSD64V4F3
Block Diagram
A0~A12,
BA0,BA1
DQ0~DQ63
/RAS
/CAS
/WE
/CS0
CKE0
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
CKE
32Mx8
DDR
SDRAM
200PIN DDR400 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
32Mx8
DDR
SDRAM
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
32Mx8
DDR
SDRAM
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
CKE
/CS
32Mx8
DDR
SDRAM
CK,/CK
CK,/CK
CK,/CK
CKE
CKE
CK0,/CK0
CK1,/CK1
DM0
DQS0
DM2
DQS2
DM4
DQS4
DM6
DQS6
CK,/CK
CK,/CK
CK,/CK
DQS
DM
DM
DM
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
CKE
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
CKE
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
CKE
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
CKE
32Mx8
DDR
SDRAM
32Mx8
DDR
SDRAM
32Mx8
DDR
SDRAM
32Mx8
DDR
SDRAM
DQS
DQS
DM
DM1
DQS1
DM3
DQS3
DM5
DQS5
DM
DQS
DM
DM7
DQS7
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
32Mx8
DDR
SDRAM
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
DM
CKE
32Mx8
DDR
SDRAM
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
/CS
DM
CKE
32Mx8
DDR
SDRAM
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/CAS
/WE
CKE
/CS
32Mx8
DDR
SDRAM
CK,/CK
CK,/CK
CK,/CK
DQS
DQS
CKE
DM0
DQS0
DM2
DQS2
DM4
DQS4
DM6
DQS6
CK,/CK
CK,/CK
CK,/CK
/RAS
/CAS
/WE
/CS
DM
CKE
/RAS
/CAS
/WE
/CS
CKE
/RAS
/CAS
/WE
/CS
CKE
DM
/RAS
/CAS
/WE
/CS
CKE
32Mx8
DDR
SDRAM
32Mx8
DDR
SDRAM
32Mx8
DDR
SDRAM
32Mx8
DDR
SDRAM
DQS
DQS
DQS
DM
DM1
Serial EEPROM
SCL
SCL
SDA
SDA
DQS1
DM3
DQS3
DM5
DQS5
DM7
DQS7
A0
A1
A2
SA0 SA1 SA2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
Transcend Information Inc.
4
DM
DQS
CK,/CK
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
DQS
DM
DM
/CS1
CKE1
DQS
/CS
CK,/CK
DQS
CK,/CK
CK,/CK
DQS
DQS
DQS
DM
DM
TS64MSD64V4F3
ABSOLUTE MAXIMUM RATINGS
200PIN DDR400 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply to Vss
VDD, VDDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55~+150
°C
Power dissipation
P
D
9.5
W
Short circuit current
I
OS
50
mA
Mean time between failure
MTBF
50
year
Temperature Humidity Burning
THB
85°C/85%, Static Stress
°C-%
Temperature Cycling Test
TC
0°C ~ 125°C Cycling
°C
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage
VDD
2.5
2.7
V
I/O Supply voltage
VDDQ
2.5
2.7
V
I/O Reference voltage
VREF
V
DDQ
/2-50mV V
DDQ
/2+50mV
V
1
I/O Termination voltage
VTT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
VIH
(DC)
V
REF
+0.15
V
DDQ
+0.3
V
4
Input logic low voltage
VIL
(DC)
-0.3
V
REF
-0.15
V
4
Input Voltage Level, CK and /CK inputs
VIN
(DC)
-0.3
V
DDQ
+0.3
V
Input Differential Voltage, CK and /CK inputs
VID
(DC)
0.3
V
DDQ
+0.6
V
3
Input crossing point voltage, CK and /CK inputs
VIX
(DC)
1.15
1.35
V
5
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current (Normal strength driver)
I
OH
-16.8
mA
VOUT= 1.95
Output Low Current (Normal strength driver)
I
OL
16.8
mA
VOUT= 0.35
Output High Current (Half strength driver)
I
OH
-9
mA
VOUT= VTT + 0.45V
Output High Current (Half strength driver)
I
OL
9
mA
VOUT= VTT - 0.45V
Note: 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and
DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on
VREF and internal DRAM noise coupled. TO VREF, both of which may result in VREF noise. VREF should be
de-coupled with an inductance of <=3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to
be set equal to VREF, and must track variations in the DC level of VREF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on /CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or
the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been
bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc
创意市集
