TS68C000
Low Power HCMOS 16-/32-bit
Hi-Rel Microprocessor
Datasheet
Features
•
•
•
•
•
•
•
•
•
16-/32-bit Data and Address Register
16-Mbyte Direct Addressing Range
56 Powerful Instruction Types
Operations on Five Main Data Types
Memory Mapped Input/Output
14 Addressing Modes
Three Available Versions: 8 MHz/10 MHz and 12.5 MHz
Military Temperature Range: -55/+125°C
Power Supply: 5V
DC
± 10%
Description
The TS68C000 reduced power consumption device dissipates an order of magnitude less power than the HMOS TS68000.
The TS68C000 is an implementation of the TS68000 16/32 microprocessor architecture. The TS68C000 has a 16-bit data
bus and 24-bit address bus while the full architecture provides for 32-bit address and data-buses. It is completely code-
compatible with the HMOS TS68000, TS68008 8-bit data bus implementation of the TS68000 and the TS68020 32-bit
implementation of the architecture. Any user-mode programs written using the TS68C000 instruction set will run
unchanged on the TS68000, TS68008 and TS68020. This is possible because the user programming model is identical for
all processors and the instruction sets are proper sub-sets of the complete architecture.
Screening/Quality
This product is manufactured in full compliance with:
•
MIL-STD-883 class B
•
DESC drawing 5962-89462
•
e2v standards
C Suffix
DIL 64
Ceramic Package
F Suffix
CQFP 68
Ceramic Quad Flat Pack (on reque
E Suffix
LCCC 68
Leadless Ceramic Chip Carrier
R Suffix
PGA 68
Pin Grid Array
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e2v semiconductors SAS 2007
0853B–HIREL–09/07
TS68C000
1. General Description
1.1
Introduction
This detail specification contains both a summary of the TS68C000 as well as detailed set of paramet-
rics. The purpose is twofold to provide an instruction to the TS68C000 and support for the sophisticated
user. For detail information on the TS68C000, refer to "68000 16-bit microprocessor user’s manual".
1.2
Detailed Block Diagram
The functional block diagram is given in
Figure 1-1
below.
Figure 1-1.
Status
and
Control
Clock
Block Diagram
Clock Gen.
and
Timing Control
Interrupt
Control
Instruction
Decode
Bus
Control
Logic
VCC
VGND
Control
Store
M Store
N Store
Alu Function
and Reg
Selection
System
Control
Signals
Internal
Control
bus
Instruction
Register
DATA BUS
Data
Bus
Buffer
16-bit
Data
Bus
Address High
Execution Unit
and Registers
16-bit
Alu
Address Low
Execution Unit
and Registers
16-bit
Alu
Data Execution
Unit
and Registers
16-bit
Alu
Addr.
Bus
Buffer
32-bit
Address
Bus
ADDRESS BUS
2
0853B–HIREL–09/07
e2v semiconductors SAS 2007
TS68C000
1.3
Pin Assignments
Figure 1-2.
64-lead Dual-in-Line Package
Index
D4
D3
D2
D1
D0
AS
UDS
LDS
R/W
DTACK
BG
BGACK
BR
VCC
CLK
GND
HALT
RESET
VMA
E
VPA
BERR
IPL2
IPL1
IPL0
FC2
FC1
FC0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TOP VIEW
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
3
0853B–HIREL–09/07
e2v semiconductors SAS 2007
TS68C000
Figure 1-3.
68-terminal Pin Grid Array
L
J
H
NC
FC2 FC0
A1
A3
A2
A4
A5
A6
A7
A9
NC
BERR IPL0 FC1 NC
E
IPL2 IPL1
A8 A10 A11 A14
A13 A12 A16
A15 A17
G
VMA VPA
F
HALT RESET
E
D
C
BGACK BG
B
A
R/W
D3
D4
5
D6
D5
6
DTACK LDS UDS D0
NC
1
AS
2
D1
3
D2
4
CLK GND
BR VCC
BOTTOM VIEW
A18 A19
VCC A20
GND A21
D13 A23 A22
D9 D11 D14 D15
D7
7
D8
8
D10 D12
9
10
Index
Figure 1-4.
68-lead Quad Pack
Index
R/W
LDS
UDS
AS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
DTACK
BG
BGACK
BR
VCC
CLK
GND
GND
NC
HALT
RESET
VMA
E
VPA
BERR
IPL2
IPL1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
TOP VIEW
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D13
D14
D15
GND
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
4
0853B–HIREL–09/07
IPL0
FC2
FC1
FC0
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
e2v semiconductors SAS 2007
TS68C000
Figure 1-5.
68-ceramic Quad Flat Pack
Index
68
1
R/W
LDS
LDS
AS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
52
51
DTACK
BG
BGACK
BR
VCC
CLK
GND
GND
NC
HALT
RESET
VMA
E
VPA
BERR
IPL2
IPL1
TOP VIEW
17
18
34
IPL0
FC2
FC1
FC0
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D13
D14
D15
GND
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
35
1.4
Terminal Designations
The function, category and relevant symbol of each terminal of the device are given in the following
table.
Table 1-1.
Symbol
V
CC
V
SS(1)
FC0 to FC2
IPL0 to IPL2
A1 to A23
AS
R/W
Outputs
UDS
LDS
DTACK
BR
Inputs
BGACK
BG
Bus arbitration control
Output
Input
Asynchronous bus control
Terminal Designations
Function
Power supply (2 terminals)
Power supply (2 terminals)
Processor status
Interrupt control
Address bus
Category
Supply
Terminals
Outputs
Inputs
Outputs
5
0853B–HIREL–09/07
e2v semiconductors SAS 2007
