TS68EN360
32:BIT QUAD INTEGRATED
COMMUNICATION CONTROLLER
DESCRIPTION
The TS68EN360 QUad Integrated Communication Controller
(QUICCt) is a versatile one-chip integrated microprocessor and
peripheral combination that can be used in a variety of controller
applications. It particularly excels in communications activities.
The QUICC (pronounced ”quick”) can be described as a next-
generation TS68302 with higher performance in all areas of
device operation, increased flexibility, major extensions in capa-
bility, and higher integration. The term ”quad” comes from the fact
that there are four serial communications controllers (SCCs) on
the device; however, there are actually seven serial channels:
four SCCs, two serial management controllers (SMCs), and one
seral peripheral interface (SPI).
MAIN FEATURES
H
CPU32+ Processor (4.5 MIPS at 25 MHz)
- 32-Bit Version of the CPU32 Core (Fully Compatible with
the CPU32)
- Background Debug Mode
- Byte-Misaligned Addressing
R suffix
PGA 241
Ceramic Pin Grid Array
Cavity Up
H
Up to 32-Bit Data Bus
(Dynamic Bus Sizing for 8 and 16 Bits)
H
Up to 32 Address Lines (At Least 28 Always Available)
H
Complete Static Design (0-25 MHz Operation)
H
Slave Mode To Disable CPU32+
(Allows Use with External Processors)
- Multiple QUICCs Can Share One System Bus (One Master)
- TS68040 Companion Mode Allows QUICC To Be an
TS68040 Companion Chip and Intelligent Peripheral
(22 MIPS at 25 MHz)
- Peripheral device of TSPC603e (see DC415/D note)
H
Four General-Purpose Timers
- Superset of MC68302 Timers
- Four 16-Bit Timers or Two 32-Bit Timers
- Gate Mode Can Enable/Disable Counting
H
H
H
H
H
H
H
H
H
H
Two Independent DMAs (IDMAs)
System Integration Module (SIM60)
Communications Processor Module (CPM)
Four Baud Rate Generators
Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full
10-Mbps Support) (see § 6.4)
Two SMC
V
CC
=
+5 V
±
5 %
f
max
=
25 MHz and 33 MHz
Military temperature range : –55°C < T
C
< +125°C
P
D
=
1.4 W
at 25 MHz ; 5.25 V
2 W
at 33 MHz ; 5.25 V
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
Cavity Down
SCREENING / QUALITY
This product is manufactured in full compliance with :
H
MIL-STD-883 (class B)
H
QML (class Q)
H
or according to TCS standard
1/72
April 1999
TS68EN360
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . 3
1.
2.
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.
2.2.
3.
3.1.
3.2.
241 Lead Pin Grid Array (PGA) . . . . . . . . . . . . 4
240 Lead Cerquad . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Signal Groups . . . . . . . . . . . . . . . . . . 6
Signal Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.11. 040 Bus Type Sram/Dram Cycles AC Electrical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.12. IDMA AC Electrical Specifications . . . . . . . . 47
5.13. PIP/PIO Electrical Specifications . . . . . . . . . . 48
5.14. Interrupt Controller AC Electrical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.15. Baud Rate Generator AC Electrical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.16. Timer Electrical Specifications . . . . . . . . . . . . 51
5.17. SI Electrical Specifications . . . . . . . . . . . . . . . . 52
5.18. SCC in NMSI Mode-external Clock Electrical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 6
B. DETAILED SPECIFICATIONS . . . . . . . . 10
1.
2.
3.
SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . 10
REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.
3.2.
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Design and Construction . . . . . . . . . . . . . . . . . 10
3.2.1. Terminal connections . . . . . . . . . . . . . . . . . . . 10
3.2.2. Lead material and finish . . . . . . . . . . . . . . . . . 10
3.2.3. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.19. SCC in NMSI Mode-internal Clock Electrical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.20. Ethernet Electrical Specifications . . . . . . . . . . 58
5.21. SMC Transparent Mode Electrical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.22. SPI Master Electrical Specifications . . . . . . . . 61
5.23. SPI Slave Electrical Specifications . . . . . . . . . 62
5.24. JTAG Electrical Specifications . . . . . . . . . . . . 63
6.
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . 65
6.1.
6.2.
6.3.
6.4.
6.5.
CPU32+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . 65
System Integration Module (SIM60) . . . . . . . 65
Communications Processor Module (CPM) . 65
Ethernet on QUICC . . . . . . . . . . . . . . . . . . . . . 65
Upgrading Designs from the TS68302 . . . . . . 66
6.5.1. Architectural Approach . . . . . . . . . . . . . . . . . 66
6.5.2. Hardware Compatibility Issues . . . . . . . . . . . 66
6.5.3. Software Compatibility Issues . . . . . . . . . . . . 67
3.3.
Electrical characteristics . . . . . . . . . . . . . . . . . . 10
3.3.1. Absolute maximum ratings . . . . . . . . . . . . . . . 10
3.3.2. Recommended conditions of use . . . . . . . . . . 11
3.4.
3.5.
3.6.
3.7.
4.
5.
Thermal characteristics . . . . . . . . . . . . . . . . . . . 11
Power considerations . . . . . . . . . . . . . . . . . . . . 11
Mechanical and environment . . . . . . . . . . . . . . 11
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
QUALITY CONFORMANCE INSPECTION . . . . 12
ELECTRICAL CHARACTERISTICS . . . . . . . . . . 12
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
General requirements . . . . . . . . . . . . . . . . . . . . 12
Static characteristics . . . . . . . . . . . . . . . . . . . . . 13
Dynamic characteristics . . . . . . . . . . . . . . . . . . 14
AC Power Dissipation . . . . . . . . . . . . . . . . . . . . 15
Ac Electrical Specifications Control Timing . 16
External Capacitor For PLL . . . . . . . . . . . . . . 17
Bus Operation AC Timing Specifications . . . . 18
Bus Operation - Dram Accesses AC Timing
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
040 Bus Type Slave Mode Bus Arbitration AC
Electrical Specifications . . . . . . . . . . . . . . . . . . 37
8.
9.
7.
PREPARATION FOR DELIVERY . . . . . . . . . . . . . 67
7.1.
7.2.
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Certificate of compliance . . . . . . . . . . . . . . . . . 67
HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . 68
9.1.
9.2.
241 pins - PGA . . . . . . . . . . . . . . . . . . . . . . . . 68
240 PINS - CERQUAD . . . . . . . . . . . . . . . . . 69
10. ORDERING INFORMATION . . . . . . . . . . . . . . . . . 70
10.1. Hi-REL product . . . . . . . . . . . . . . . . . . . . . . . 70
10.2. Standard product . . . . . . . . . . . . . . . . . . . . . . . . 70
5.10. 040 Bus Type Slave Mode Internal
Read/Write/Iack Cycles AC Electrical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2/72
TS68EN360
A. GENERAL DESCRIPTION
1. INTRODUCTION
QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the TS68300 family. Like other members of the TS68300 family,
the QUICC incorporates the intermodule bus (IMB). (The TS68302 is an exception, having an 68000 bus on chip). The IMB provides a
common interface for all modules of the TS68300 family, which allows the development of new devices more quickly by using the library of
existing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to
implement this option.
The QUICC is comprised of three modules : the CPU32+ core, the SIM60, and the CPM. Each module utilizes the 32-bit IMB.
The TS68EN360 QUICC block diagram is shown in Figure 1.
SIM 60
SYSTEM
PROTECTION
PERIODIC
TIMER
CLOCK
GENERATION
OTHER
FEATURES
IMB (32BIT)
JTAG
BREAKPOINT
LOGIC
DRAM
CONTROLLER
AND
CHIP SELECTS
EXTERNAL
BUS
INTERFACE
CPU32+
CORE
SYSTEM
I/F
CPM
COMMUNICATIONS PROCESSOR
2,5–KBYTE
RISC
DUAL–PORT
CONTROLLER
RAM
TWO
IDMAs
FOURTEEN SERIAL
DAMs
SEVEN
SERIAL
CHANNELS
INTERRUPT
CONTROLLER
FOUR
GENERAL–
PURPOSE
TIMERS
TIMER SLOT
ASSIGNER
OTHER
FEATURES
Figure 1:
QUICC Block Diagram
3/72
TS68EN360
2. PIN ASSIGNMENTS
2.1. 241-Lead Pin Grid Array (PGA)
T
PA15 PA12
S
D2
R
D4
Q
D7
P
D10
N
D13
M
D16
L
D19
K
CLKO2 Vcc
J
CLKO1 D20
H
D21
G
D24
F
D27
E
D30
D
FC2
C
SIZ1
B
SIZ0
A
XTAL
1
2
NC4
3
A26
4
A24
5
A21
6
A18
7
A15
8
A12
9
A11
10
A9
11
A6
12
A3
13
A2
14
TRIS
15
CS6
16
CS3
17
CS0
18
A28 MODCK0 GND
A25
A22
A19
A16
A13
A10
A7
A5
A1
IRQ7
CS5
CS2
CAS2 CAS1
A29 EXTAL MODCK1 A27
A23
A20
A17
A14
A8
A4
A0
CS7
CS4
CS1 CAS3 FREEZE DS
FC1
A30
XFC
Vcc
GND
GND
Vcc
Vcc
GND
GND
GND
GND
Vcc
GND CAS0
R/W DSACK0
FC3
FC0
A31 Vccsyn GNDsyn
GND
Vcc GNDs1 Vcc
NC3 DSACK1 PRTY3
D29
D31
GND
GND
Vcc
GND PRTY2 PRTY1 PRTY0
D26
D28
Vcc
Vcc IPIPE0
AS
IPIPE1
D23
D25
GND
GNDs2 NC2 BCLRO OE
D22
GND
Vcc
GND Vccclk
GNDclk
TS68EN360
(BOTTOM VIEW)
GND
GND IFETCH NC1
BR
Vcc
Vcc
IRQ4 BGACK BG
D18
D17
Vcc
GND TRST BKPT IRQ6
D15
D14
GND
Vcc
TD1
TCK RESETH
D12
D11
GND
GND
GND
GND AVEC TDO
TMS
D9
D8
GND
Vcc
GND
NC
Vcc
GND
GND HALT RMC PERR
D6
D5
GND
GND
GND
Vcc
Vcc
GND
GND
Vcc
Vcc
GND
GND
GND
IRQ5 BERR RESETS
D3
D1
PA14 PA11
PA8
PA4
PA0
PB14
PB9
PB6
PB3
PB0
PC8
PC4
PC0
IRQ3 IRQ1
D0
PA13 PA10
PA7
PA5
PA1
PB16 PB13 PB10
PB7
PB4
PB1
PC10
PC7
PC3
PC1
IRQ2
PA9
PA6
PA3
PA2
PB17 PB15 PB12 PB11
PB8
PB5
PB2
PC11
PC9
PC6
PC5
PC2
Note : Pin P9 ”NC” is for guide purposes only.
Figure 2:
4/72
TS68EN360
2.2. 240-Lead Cerquad
GNDs1
CAS3
CAS2
Vcc
CAS1
GND
CAS0
FREEZE
DS
GND
R/W
NC3
Vcc
DSACK0
GND
DSACK1
GND
PRTY3
PRTY2
GND
Vcc
PRTY1
PRTY0
IPIPE0
AS
GNDs2
IPIPE1
Vcc
NC2
BCLRO
GND
OE
IFETCH
NC1
BR
Vcc
GND
BG
BGACK
Vcc
IRQ4
IRQ6
GND
BKPT
RESETH
TRST
TCK
TMS
TDI
TDO
PERR
GND
AVEC
RMC
Vcc
RESETS
HALT
GND
BERR
IRQ1
180
181
CS0
CS1
CS2
CS3
Vcc
GND
CS4
CS5
CS6
CS7
IRQ7
TRIS
A0
A1
GND
A2
A3
Vcc
A4
A5
GND
A6
A7
Vcc
GND
A8
A9
GND
A10
A11
Vcc
A12
A13
GND
A14
A15
A16
A17
A18
GND
A19
A20
A21
Vcc
A22
A23
A24
GND
A25
A26
A27
NC4
GND
MODCK1
MODCK0
XTAL
EXTAL
GNDsyn
XFC
Vccsyn
170
160
150
140
130
121
120
190
110
200
100
210
TS68EN360
(TOP VIEW)
90
220
80
230
70
PIN ONE INDICATOR
240
1
10
20
30
40
50
60
61
A28
A29
GND
A30
A31
Vcc
SIZ0
SIZ1
FC0
GND
FC1
FC2
FC3
Vcc
GND
D31
D30
D29
GND
D28
D27
D26
Vcc
D25
D24
D23
GND
D22
D21
D20
CLKO1
Vccclk
GNDclk
CLKO2
D19
D18
D17
GND
D16
D15
Vcc
D14
D13
D12
GND
D11
D10
D9
D8
D7
GND
D6
D5
Vcc
D4
D3
D2
GND
D1
D0
IRQ5
IRQ3
IRQ2
PC0
PC1
PC2
GND
PC3
PC4
PC5
PC6
Vcc
PC7
PC8
PC9
PC10
GND
PC11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
GND
PB7
PB8
PB9
PB10
Vcc
PB11
PB12
PB13
PB14
GND
PB15
PB16
PB17
PA0
GND
Vcc
PA1
PA2
PA3
PA4
GND
PA5
PA6
PA7
PA8
Vcc
PA9
PA10
PA11
PA12
GND
PA13
PA14
PA15
Figure 3:
5/72
ARM技术
