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TSB83C196KD20

Microcontroller, 16-Bit, MROM, 8096 CPU, 20MHz, CMOS, PQFP80, SQFP-80

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:Intel(英特尔)

厂商官网:http://www.intel.com/

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器件参数
参数名称
属性值
厂商名称
Intel(英特尔)
零件包装代码
QFP
包装说明
SQFP-80
针数
80
Reach Compliance Code
compliant
具有ADC
YES
地址总线宽度
16
位大小
16
CPU系列
8096
最大时钟频率
20 MHz
DAC 通道
NO
DMA 通道
NO
外部数据总线宽度
16
JESD-30 代码
S-PQFP-G80
长度
12 mm
I/O 线路数量
48
端子数量
80
最高工作温度
85 °C
最低工作温度
-40 °C
PWM 通道
YES
封装主体材料
PLASTIC/EPOXY
封装代码
LFQFP
封装等效代码
QFP80,.55SQ,20
封装形状
SQUARE
封装形式
FLATPACK, LOW PROFILE, FINE PITCH
电源
5 V
认证状态
Not Qualified
RAM(字节)
1024
ROM(单词)
32768
ROM可编程性
MROM
座面最大高度
1.7 mm
速度
20 MHz
最大压摆率
92 mA
最大供电电压
5.5 V
最小供电电压
4.5 V
标称供电电压
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子形式
GULL WING
端子节距
0.5 mm
端子位置
QUAD
宽度
12 mm
uPs/uCs/外围集成电路类型
MICROCONTROLLER
文档预览
8XC196KD/8XC196KD20
COMMERCIAL CHMOS MICROCONTROLLER
87C196KD/32 Kbytes of On-Chip OTPROM
83C196KD/32 Kbytes of ROM
16 MHz and 20 MHz Available
1000 Byte Register RAM
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
Peripheral Transaction Server
1.4 µs 16 x 16 Multiply (20 MHz)
2.4 µs 32/16 Divide (20 MHz)
Powerdown and Idle Modes
Five 8-Bit I/O Ports
16-Bit Watchdog Timer
Dynamically Configurable 8-Bit or
16-Bit Buswidth
Full Duplex Serial Port
High Speed I/O Subsystem
16-Bit Timer
16-Bit Up/Down Counter with Capture
3 Pulse-Width-Modulated Outputs
Four 16-Bit Software Timers
8- or 10-Bit A/D Converter with
Sample/Hold
HOLD/HLDA Bus Protocol
OTP One-Time Programmable Version
Extended Temperature Available
The 8XC196KD 16-bit microcontroller is a high performance member of the MCS
®
96 microcontroller family.
The 8XC196KD is an enhanced 80C196KC device with 1000 bytes RAM, 16 MHz operation and an optional
32 Kbytes of ROM/EPROM. Intel’s CHMOS III process provides a high performance processor along with low
power consumption.
The 8XC196KD has a maximum guaranteed frequency of 16 MHz. The 8XC196KD20 has a maximum guaran-
teed frequency of 20 MHz. Unless otherwise noted, all references to the 8XC196KD also refer to the
8XC196KD20.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/ D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temp-
erature range of the 0°C to +70°C. With the extended (express) temperature range option, operational charac-
teristics are guaranteed over the temperature range of -40°C to +85°C. Unless otherwise noted, the specifica-
tions are the same for both options.
See the packaging information for extended temperature designators.
*Other brands and names may be claimed as the property of others.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 2004
July 2004
Order Number: 272145-005
8XC196KD/8XC196KD20
272145 ±1
Figure 1. 8XC196KD Block Diagram
87C196KD ENHANCED FEATURE SET
OVER THE 87C196KC
1. The 87C196KD has twice the RAM and twice the
OTPROM space of the 87C196KC.
2. The vertical windowing scheme has been extend-
ed to allow all 1000 bytes of register RAM to be
windowed into the lower register file.
IOC3 (0CH HWIN1 READ/WRITE)
272145 ±2
NOTE:
RSVÐReserved bits must be
e
0
Figure 2. 87C196KD New SFR Bit
(CLKOUT Disable)
2
8XC196KD/8XC196KD20
8XC196KD VERTICAL WINDOWING
MAP
Table 1. 128-Byte Windows
Address to
Remap
0380H
0300H
0280H
0200H
0180H
0100H
0080H
0000H
Device
Series
KD
KD
KD
KD
KC, KD
KC, KD
KC, KD
KC, KD
WSR Contents
X001 0111B
e
17H
X001 0110B
e
16H
X001 0101B
e
15H
X001 0100B
e
14H
X001 0011B
e
13H
X001 0010B
e
12H
X001 0001B
e
11H
X001 0000B
e
10H
Table 3. 32-Byte Windows
Address to
Remap
03E0H
03C0H
03A0H
0380H
0360H
0340H
0320H
0300H
02E0H
02C0H
02A0H
0280H
0260H
0240H
0220H
0200H
01E0H
01C0H
01A0H
0180H
0160H
0140H
0120H
0100H
00E0H
00C0H
00A0H
0080H
0060H
0040H
0020H
0000H
Device
Series
KD
KD
KD
KD
KD
KD
KD
KD
KD
KD
KD
KD
KD
KD
KD
KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
WSR Contents
X101 1111B
e
5FH
X101 1110B
e
5EH
X101 1101B
e
5DH
X101 1100B
e
5CH
X101 1011B
e
5BH
X101 1010B
e
5AH
X101 1001B
e
59H
X101 1000B
e
58H
X101 0111B
e
57H
X101 0110B
e
56H
X101 0101B
e
55H
X101 0100B
e
54H
X101 0011B
e
53H
X101 0010B
e
52H
X101 0001B
e
51H
X101 0000B
e
50H
X100 1111B
e
4FH
X100 1110B
e
4EH
X100 1101B
e
4DH
X100 1100B
e
4CH
X100 1011B
e
4BH
X100 1010B
e
4AH
X100 1001B
e
49H
X100 1000B
e
48H
X100 0111B
e
47H
X100 0110B
e
46H
X100 0101B
e
45H
X100 0100B
e
44H
X100 0011B
e
43H
X100 0010B
e
42H
X100 0001B
e
41H
X100 0000B
e
40H
Window in Lower Register File: 80H ±FFH
Table 2. 64-Byte Windows
Address to
Remap
03C0H
0380H
0340H
0300H
02C0H
0280H
0240H
0200H
01C0H
0180H
0140H
0100H
00C0H
0080H
0040H
0000H
Device
Series
KD
KD
KD
KD
KD
KD
KD
KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
WSR Contents
X010 1111B
e
2FH
X010 1110B
e
2EH
X010 1101B
e
2DH
X010 1100B
e
2CH
X010 1011B
e
2BH
X010 1010B
e
2AH
X010 1001B
e
29H
X010 1000B
e
28H
X010 0111B
e
27H
X010 0110B
e
26H
X010 0101B
e
25H
X010 0100B
e
24H
X010 0011B
e
23H
X010 0010B
e
22H
X010 0001B
e
21H
X010 0000B
e
20H
Window in Lower Register File: C0H±FFH
Window in Lower Register File: E0H±FFH
3
8XC196KD/8XC196KD20
PROCESS INFORMATION
This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliabili-
ty information is available in
the
Intel® Quality
System Handbook:
http://developer.intel.com/design/quality/quality.htm
Table 5. 8XC196KD Memory Map
Description
External Memory or I/O
Internal ROM/OTPROM or External
Memory (Determined by EA)
Reserved. Must contain FFH.
(Note 5)
PTS Vectors
Upper Interrupt Vectors
Address
0FFFFH
0A000H
9FFFH
2080H
207FH
205EH
205DH
2040H
203FH
2030H
202FH
2020H
201FH
201AH
2019H
2018H
2017H
2014H
2013H
2000H
1FFFH
1FFEH
1FFDH
0400H
03FFH
0018H
0017H
0000H
x
x
x
ROM/OTPROM Security Key
Reserved. Must contain FFH.
(Note 5)
Reserved. Must Contain 20H
(Note 5)
CCB
Reserved. Must contain FFH.
(Note 5)
Lower Interrupt Vectors
Port 3 and Port 4
External Memory
1000 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1, 3)
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 3. The 8XC196KD Family Nomenclature
Table 4. Thermal Characteristics
Package
Type
PLCC
QFP
SQFP
θ
ja
35
°
C/W
56
°
C/W
68
°
C/W
θ
jc
13
°
C/W
12
°
C/W
15.5
°
C/W
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel
Packaging Handbook
(order number 240800) for a
description of Intel’s thermal impedance test methodology.
NOTES:
1. Code executed in locations 0000H to 03FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC for SFR descriptions.
5.
WARNING:
Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
4
8XC196KD/8XC196KD20
272145 – 3
Figure 4. 68-Pin PLCC Package
5
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