TSC80251G2D
8/16-bit Microcontroller
Interfaces
1. Description
The TSC80251G2D products are derivatives of the
T
EMIC
Microcontroller family based on the 8/16-bit
C251 Architecture. This family of products is tailored
to 8/16-bit microcontroller applications requiring an
increased instruction throughput, a reduced operating
frequency or a larger addressable memory space. The
architecture can provide a significant code size reduction
when compiling C programs while fully preserving the
legacy of C51 assembly routines.
The TSC80251G2D derivatives are pin and software
compatible with standard 80C51/Fx/Rx/Rx+ with
extended on-chip data memory (1 Kbyte RAM) and up
to 256 Kbytes of external code and data. Additionally,
the TSC83251G2D and TSC87251G2D provide on-chip
code memory: 32 Kbytes ROM and 32 Kbytes EPROM/
OTPROM respectively.
They provide transparent enhancements to Intel’s
8xC251Sx family with an additional Synchronous Serial
Link Controller (SSLC supporting I
2
C,
µWire
and SPI
protocols), a Keyboard interrupt interface, a dedicated
Baud Rate Generator for UART, and Power Management
features.
TSC80251G2D derivatives are optimized for speed and
for low power consumption on a wide voltage range.
with
Serial
Communication
Note:
This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request
the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide.
2. Typical Applications
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ISDN Terminals
High-Speed Modems
PABX (SOHO)
Line Cards
DVD ROM and Players
Printers
Plotters
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Scanners
Banking Machines
Barcode Readers
Smart Cards Readers
High-End Digital Monitors
High-End Joysticks
Rev. A - May 7, 1999
1
TSC80251G2D
3. Features
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Pin and Software Compatibility with Standard 80C51
Products and 80C51Fx/Rx/Rx+
Plug-In Replacement of Intel’s 8xC251Sx
C251 core: Intel’s MCS
®
251 D-step Compliance
•
40-byte register file
•
Registers accessible as Bytes, Words or Dwords
•
Three-stage instruction pipeline
•
16-bit internal code fetch
Enriched C51 Instruction Set
•
16-bit and 32-bit ALU
•
Compare and conditional jump instructions
•
Expanded set of move instructions
•
16-bit watchdog timer/counter capability
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Secure 14-bit Hardware Watchdog Timer
Power Management
•
Power-On reset (integrated on the chip)
•
Power-Off flag (cold and warm resets)
•
Software programmable system clock
•
Idle mode
•
Power-Down mode
Keyboard Interrupt Interface on Port 1
Non Maskable Interrupt Input (NMI)
Real-Time Wait States Inputs (WAIT#/AWAIT#)
ONCE mode and full speed Real-Time In-Circuit
Emulation support (Third Party Vendors)
High Speed Versions:
•
4.5 to 5.5 V
•
16 MHz and 24 MHz
•
Typical operating current: 35 mA @ 24 MHz
24 mA @ 16 MHz
•
Typical power-down current: 2
µA
Low Voltage Version:
•
2.7 to 5.5 V
•
16 MHz
•
Typical operating current: 11 mA @ 3V
•
Typical power-down current: 1
µA
Temperature Ranges:
•
Commercial (0°C to +70°C)
•
Industrial (-40°C to +85°C)
•
Option: extended range (-55°C to +125°C)
Packages:
•
PDIL 40, PLCC 44 and VQFP 44
•
CDIL 40 and CQPJ 44 with window
•
Options: known good dice and ceramic packages
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Linear Addressing
1 Kbyte of On-Chip RAM
External Memory Space (Code/Data) Programmable
from 64 Kbytes to 256 Kbytes
TSC87251G2D: 32 Kbytes of On-Chip EPROM/
OTPROM
•
SINGLE PULSE Programming Algorithm
TSC83251G2D: 32 Kbytes of On-Chip Masked ROM
TSC80251G2D: ROMless Version
Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of
the standard 80C51)
Serial I/O Port: full duplex UART (80C51
compatible) with independent Baud Rate Generator
SSLC: Synchronous Serial Link Controller
•
I
2
C multi-master protocol
• µWire
and SPI master and slave protocols
Three 16-bit Timers/Counters (Timers 0, 1 and 2 of
the standard 80C51)
EWC: Event and Waveform Controller
•
Compatible with Intel’s Programmable Counter
Array (PCA)
•
Common 16-bit timer/counter reference with four
possible clock sources (Fosc/4, Fosc/12, Timer 1
and external input)
•
Five modules, each with four programmable
modes:
- 16-bit software timer/counter
- 16-bit timer/counter capture input and
software pulse measurement
- High-speed output and 16-bit software pulse
width modulation (PWM)
- 8-bit hardware PWM without overhead
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Rev. A - May 7, 1999
TSC80251G2D
4. Block Diagram
P3(A16)
P2(A15-8)
P1(A17)
P0(AD7-0)
PSEN#
PORTS 0-3
ALE/PROG#
16-bit Memory Code
EA#/VPP
16-bit Memory Address
Event and Waveform
Controller
ROM
EPROM
OTPROM
32 Kbytes
RAM
1 Kbyte
Timers 0, 1 and 2
UART
Baud Rate Generator
AWAIT#
Bus Interface Unit
Peripheral Interface Unit
I
2
C/SPI/µWire
Controller
Watchdog Timer
24-bit Program Counter Bus
16-bit Instruction Bus
24-bit Data Address Bus
8-bit Internal Bus
RST
Power Management
XTAL2
Clock Unit
Clock System Prescaler
8-bit Data Bus
XTAL1
Keyboard Interface
CPU
Interrupt Handler
Unit
NMI
VDD
VSS
VSS1
VSS2
Figure 1. TSC80251G2D Block Diagram
Rev. A - May 7, 1999
3
TSC80251G2D
5. Pin Description
5.1 Pinout
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1/SS#
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
TSC80251G2D
Figure 2. TSC80251G2D 40-pin DIP package
P1.4/CEX1/SS#
P1.3/CEX0
P1.2/ECI
P1.1/T2EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
TSC80251G2D
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
Figure 3. TSC80251G2D 44-pin PLCC Package
4
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
VSS2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
18
19
20
21
22
23
24
25
26
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28
Rev. A - May 7, 1999
TSC80251G2D
P1.4/CEX1/SS#
P1.3/CEX0
P1.2/ECI
P1.1/T2EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
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43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
TSC80251G2D
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
Figure 4. TSC80251G2D 44-pin VQFP Package
Table 1. TSC80251G2D Pin Assignment
DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PLCC VQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS1
P1.0/T2
P1.1/T2EX
P1.2/ECI
Name
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
VSS2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
12
13
14
15
16
17
18
19
20
21
22
DIP
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PLCC VQFP
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VSS2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN#
ALE/PROG#
NMI
EA#/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
Name
P1.3/CEX0
P1.4/CEX1/SS#
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
Rev. A - May 7, 1999
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