In addition, the TSC8051C2 has 2 software selectable
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial ports, and the interrupt
The TSC8051C2 includes the fully static 8–bit “80C51” system continue to function. In the power down mode the
CPU core with 256 bytes of RAM; 4 Kbytes of ROM; two RAM is saved and all other functions are inoperative.
16–bit timers; 12 PWM Channels; a 5 sources and 2–level The TSC8051C2 enables the users reducing a lot of
interrupt controller; a full duplex serial port; a watchdog external discrete components while bringing the
maximum of flexibility.
timer; power voltage monitor and on–chip oscillator.
The TSC8051C2 is a stand–alone high performance
CMOS 8–bit embedded microcontroller and is designed
for use in CRT monitors. It is also suitable for automotive
and industrial applications.
2. Features
D
Boolean processor
D
Fully static design
D
4K bytes of ROM
D
256 bytes of RAM
D
2 x 16–bit timer/counter
D
Programmable serial port
D
5 interrupt sources:
D
External interrupts (2)
D
Timers interrupt (2)
D
Serial port interrupt
D
Watchdog reset
D
Power Fail reset
D
On chip oscillator for crystal or ceramic resonator
D
2 power saving control modes:
D
Idle mode
D
Power–down mode
D
SYNC Processor
D
Controlled HSYNC & VSYNC outputs
D
Controlled HSYNC & VSYNC inputs
D
Clamp pulse output
D
Up to 12 programmable PWM channels with 8–bit
resolution
D
Up to 32 programmable I/O lines depending on the
package
D
40 pins DIP, 44 pins PQFP, 44 and 52 pins PLCC
packages
D
Commercial and industrial temperature ranges
D
Operating Frequency: 12 MHz to 16 MHz
MATRA MHS
Rev. A (10 Jan. 97)
1
Preview
VCC
3
3
VSS
3
3
1
XTAL1
XTAL2
EA
ALE
PSEN
3 WR
3 RD
T0
TWO 16–BIT
TIMER/EVENT
COUNTER
INT0
CPU
PROGRAM
MEMORY
4k x 8 ROM
DATA
MEMORY
256 x 8 RAM
SPECIAL
EXTERNAL
INPUTS
CLAMP
PULSE
80C51 CORE
EXCLUDING
ROM/RAM
8–BIT INTERNAL BUS
0
AD0–7
2
A8–15
RST
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
WATCHDOG
TIMER
POWER
VOLTAGE
MONITOR
12 x 8–bit PWM
CHANNELS
CONTROLLED
HSYNC & VSYNC
OUTPUTS
3
P0
P1
P2
P3
TxD
RxD
3
PWM0
–
PWM7
1
PWM8
–
PWM11
3
3
3
3
VSYNC
HSYNC
VOUT
HOUT
0 ALTERNATE FUNCTION OF PORT0
1 ALTERNATE FUNCTION OF PORT1
2 ALTERNATE FUNCTION OF PORT2
3 ALTERNATE FUNCTION OF PORT3
Figure 1. TSC8051C2 block diagram.
2
MATRA MHS
Rev. A (10 Jan. 97)
Preview
6
P1.4/CPO
P1.5
P1.6
P1.7
RST
P3.0/RXD
P3.1/TXD
P3.2/INT0/VSYNC
P3.3/INT1/VOUT
P3.4/TO/HSYNC
P3.5/T1/HOUT
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE
PSEN
PWM7 *
PWM6 *
PWM5 *
PWM4 *
PWM3 *
PWM2 *
PWM1 *
PWM0 *
P1.5
P1.6
P1.7
RST
P3.0/RXD
NC
P3.1/TXD
P3.2/INT0/VSYNC
PWM7*
PWM6*
PWM5*
7
8
9
10
11
12
13
14
15
16
17
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
P0.4
P0.5
P0.6
P0.7
EA
NC
ALE
PSEN
PWM7*
PWM6*
PWM5*
DIL 40
PLCC 44
34
33
32
31
30
29
18 19 20 21 22 23 24 26 26 27 28
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P1.2/PWM10
P1.1/PWM9
P1.0/PWM8
VCC
P0.0
P0.1
P0.2
4
3
2
1
52 51 50 49 48 47
46
45
44
43
42
PLCC 52
41
40
39
38
37
36
35
34
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
PWM7
P2.6
PWM6
P2.5
PWM5
PWM4
*PWMx or P2.x depending on option (see ordering information)
P1.3/PWM11
NC
P1.4/CPO
7
NC
P1.5
P1.6
P1.7
RST
P3.0/RXD
P3.1/TXD
P3.2/INT0/VSYNC
P3.3/INT1/VOUT
P3.4/T0/HSYNC
P3.5/T1/HOUT
NC
P3.6/WR
8
9
10
11
12
13
14
15
16
17
18
19
20
6
5
21 22 23 24 25 26 27 28 29 30 31 32 33
P3.7/RD
XTAL2
XTAL1
VSS
PWM0
P2.1
NC
INDEX
CORNER
PWM1
P2.2
PWM2
P2.3
Figure 2. TSC8051C2 pin configurations.
PWM3
P2.4
P2.0
P0.3
P0.4
NC
PWM0*
PWM1*
PWM2*
PWM3*
PWM4*
MATRA MHS
Rev. A (10 Jan. 97)
3
Preview
Power supply voltage.
RST
A high level on this pin for two machine cycles while the
oscillator is running resets the device. An internal
pulldown resistor permits power–on reset using only a
capacitor connected to VCC.
be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL on
the data–sheet) because of the internal pullups.
Port 2 emits the high–order 8–bit address during fetches
from external Program Memory and during accesses to
external Data Memory that use 16–bit addresses. In this
application it uses strong internal pull–up when emitting
1’s.
Port 2 can sink and source 3 LS TTL loads.
PORT 0 (P0.0–P0.7)
Port 0 is an 8–bit open–drain bidirectional I/O port. Port
0 pins that have 1’s written to them float, and in that state
can be used as high–impedance inputs.
Port 0 is also the multiplexed low–order address and data
bus during access to external Program and Data memory.
In this application it uses strong internal pull–up when
emitting 1’s.
Port 0 can sink and source 8 LS TTL loads.
PORT 3 (P3.0–P3.7)
Port 3 is an 8–bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL on
the data–sheet) because of the internal pullups.
Each line on this port has 2 or 3 functions either a general
I/O or special control signal, as listed below:
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
PORT 1 (P1.0–P1.7)
Port 1 is an 8–bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL on
the data–sheet) because of the internal pullups.
Port 1 also serves 4 programmable PWM open drain
outputs and programmable open drain CPO, as listed
below:
Port Pin
P1.0
P1.1
P1.2
P1.3
P1.4
Alternate Function
RXD: serial input port.
TXD: serial output port.
INT0: external interrupt 0.
VSYNC: vertical synchro input.
INT1: external interrupt 1.
VOUT: buffered V-SYNC output.
T0: Timer 0 external input.
HSYNC: horizontal synchro input.
T1: Timer 1 external input.
HOUT: buffered H–SYNC output.
WR: external data memory write strobe.
RD: external data memory read strobe.
Alternate Function
PWM8: Pulse Width Modulation output 8.
PWM9: Pulse Width Modulation output 9.
PWM10: Pulse Width Modulation output 10.
PWM11: Pulse Width Modulation output 11.
CPO: Clamp Pulse Output.
Port 3 can sink and source 3 LS TTL loads.
PWM0–7
These eight Pulse Width Modulation outputs are true
open drain outputs and are floating after reset.
Port 1 can sink and source 3 LS TTL loads.
4
MATRA MHS
Rev. A (10 Jan. 97)
Preview
If desired, ALE operation can be disabled by setting bit
0 of SFR location AFh (MSCON). With the bit set, ALE
is active only during MOVX instruction and external
fetches. Otherwise the pin is pulled low.
XTAL1
Input to the inverting oscillator amplifier and input to the
external clock generator circuits.
EA
When the External Access input is held high, the CPU
executes out of internal program memory (unless the
Program Counter exceeds 1FFFh). When EA is held low
the CPU executes only out of external program memory.
must not be left floating.
XTAL2
Output from the inverting oscillator amplifier. This pin
should be non–connected when external clock is used.
MATRA MHS
Rev. A (10 Jan. 97)
5
Preview
