TSS902E
Viterbi and Reed–Solomon FEC Decoder
1. Description
Digital communication channels are inherently noisy, making transmission error control essential for reliable
communication at low transmit power.
The TSS902E is a single–chip Forward Error Correction decoder; it conforms to the MPEG–II transport layer protocol
specified by ISO/IEC standard and FEC requirements of Digital Video Broadcasting (DVB) specification; its typical
applications are DVB satellites, regenerative multi–media transmission satellites and military communications.
The TSS902E capabilities rely on Viterbi and Reed–Solomon decoding algorithms to achieve extremely low bit–error
rate (BER) on the transmitted data. Allowing discontinuous data blocks transmission, the TSS902E burst mode feature
is unique.
The component is made of the following blocks:
G
The inner decoder which performs the first level error detection and correction.
This unit is made of a depuncturing block, a Viterbi decoder (k=7) and a synchronization/clock controller.
G
The convolutional deinterleaver, l=12 bytes for RS (204, 188, T=8) configuration.
G
The outer decoder performs the second level error protection, using a Reed Solomon (255, 239) error correcting
process.
G
The descrambler for energy dispersal removal.
G
A micro–processor interface to setup the device and monitor the testability functions.
While monitoring the inner Viterbi decoder BER output, the phase and the depuncturing pattern are tuned until the
Viterbi decoder proper alignment is found.
The Viterbi decoder output feeds the deinterleaver and Reed–Solomon decoder synchronization module. Once the
synchronization words have been found, the deinterleaver, the outer Reed–Solomon decoder and the descrambler are
properly aligned.
Each functional block may be by–passed, giving more flexibility to a system designer.
2. Features
2.1. General
G
G
G
G
G
G
G
G
G
G
Compliant with ETS 300 421 for DVB, DVB–S.
Compliant with ISO/IEC–CD 13818–1 MPEG–II transport layer protocol.
Input code rate frequency up to 10 MBits/sec at 5V.
On–chip Bit Error Rate monitoring.
SEU immunity better than 30 MeV/mg/cm
2
Total dose better than 50 Krad (Si).
Supply voltage 3 to 5V.
Power consumption 1W at 5V / 10MHz external clock frequency (code rate 7/8).
0.6
µm
drawn CMOS, 3 metal layers.
132–pin MQFP.
2.2. Viterbi Decoder
G
Selectable code rates
1
/
2
,
2
/
3
,
3
/
4
,
5
/
6
and
7
/
8
or automatic acquisition mode
.
Rev. D
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April 1999
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TSS902E
G
Hard decision or 3–Bit soft–decision decoder inputs.
G
Constraint length k = 7.
G
E
b
/N
0
for BER 2.10
–4
(code rate
1
/
2
) 3.5 dB.
2.3. Synchronization controller
G
Automatic synchronization capabilities for QPSK or BPSK.
G
Responds to inverted synchronization byte.
G
Programmable synchronization byte.
2.4. Convolutional deinterleaver
G
Error protected frame length n = 204.
G
Interleave depth I = 12.
2.5. Reed Solomon Decoder
G
Supported programmable shortened code length
G
Correction capability up to T = 8 bytes.
K = 34 to 239, T = 8.
2.6. Descrambler (Energy Dispersal)
G
Polynomial generator q(x) = X
15
+ X
14
+ 1.
G
MPEG–II inverted synchronization byte.
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TSS902E
3. Term definitions
Table 1: VITERBI
TERM
k
NAME
Encoding constraint length
Traceback depth
Puncturing
Code rate
DEFINITION
Number of input bits contributing to the convolutional code.
Length of path through the trellis over which the Viterbi
decoder computes a decoded bit value likelihood.
Transmission rate increasing process. Done by erasing some
specific code bits before data transmission.
Convolutional code input to output bits ratio.
RANGE
7
2/3, 3/4, 5/6, 7/8
Table 2: CONVOLUTIONAL DEINTERLEAVER
TERM
I
NAME
Interleaving depth
DEFINITION
Interleaved stream separation.
RANGE
12
Table 3: REED–SOLOMON
TERM
K
R
N
T
NAME
Message length
Check symbols
Codeword length
Error corrections
DEFINITION
Number of user data symbols in one message block.
Symbols appended to the user data to detect errors.
Sum of message and check symbols.
N = K + R
Maximum number of error corrections performed by the RS
decoder.
RANGE
34
p
K
p
239 bytes
16 bytes
50
p
N
p
255 bytes
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TSS902E
4. Functional description
This section describes the TSS902E device architecture and its constituents functionality.
DUP[7:0]
AD[7:0]
AS
CS
RDWRB
RESETB
TESTxxx
MICROCONTROLLER INTERFACE & TEST
IRQ
REED SOLOMON DEC.
VITERBI DECODER
DEINTERLEAVER
DEPUNCTURING
DESCRAMBLER
IEXT[2:0]
CKOCTOUT
DATAOUT[7:0]
FRAMEOUT
SYNCOUT
CKBITOUT
QEXT[2:0]
BURSTSYNCIN
CKBITEXT
SYNCHRO. CONTROL
PLL
Serial
DATAOUTS
BURSTSYNCOUT
XXXOUTF
to external filter
Figure 1: TSS902E block diagram
4.1. Synchronization
The
Synchronization Control
block is made of two parts called
Synchro–Bit
and
Synchro–Frame
which algorithms are
described hereafter.
4.1.1. The Synchro–Bit module
The
Synchro–Bit
module performs the Depuncturing block and the Viterbi decoder synchronization by monitoring the
Bit Error Rate (BER). The Viterbi
BER
calculation is done by the device during the averaging period whereas the
monitoring period can be defined by the user in order to perform off–line statistical
BER
calculations.
The Depuncturing module adds missing bits according to the code rate. Since the code rate may be unknown, the
Depuncturing block may initially use a bad rate if the automatic mode has been selected (see
RxVitControl
register –
A/M and FRE bits). Furthermore, the Depuncturing process may be uncorrectly synchronized although using the right
code rate. Both conditions will lead to an unsatisfactory
BER
value.
The Viterbi
BER
value is considered to be acceptable when it remains under the RxVitThreshold register value. This
register is actually made of several registers, each associated to one code rate value (1/2, 2/3, 3/4, 5/6 and 7/8). If
throughout the averaging period the
BER
value stays below the threshold, the
Synchro–Bit
block sets the
SBF
(Synchro
Bit Found) flag within the
RxVitStatus
register, locks the PLL and allows the
Synchro–Frame
module to start the
synchro word search.
If, on the other hand, in automatic mode, the Viterbi decoder
BER
value exceeds its programmed threshold during the
averaging period, the device will enter in
sync–bit
search mode trying to resolve at first the input data phase ambiguity
within the current code rate; if the
BER
value still is too high, the device will assume that the depuncturing process
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Rev. D
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TSS902E
was not performed on the right input bits (the bits assumed to be missing were not on the right position) and the
depuncturing state–machine will enter next state; finally, if the
BER
value still remains unacceptable, the code rate
value will be changed and the device will restart the overall search process.
Warning : if the programmed threshold value is too high, the bit synchronization may be found on a wrong position.
In automatic mode, all the threshold registers must be properly programmed according to the expected noise and code
rate. In semi–automatic mode, the user can just define the right value in the known code rate threshold register. In
manual mode, the maximum threshold value can be programmed in the code rate threshold register; the use of FRE
bit allows to find the bit synchronization for this code rate. (cf
RxVitControl
register usage)
A loss of synchronization restarts a search of frame synchro. The Data processing of blocks placed after sync–frame
block is restarted as well.
The
Synchro–Bit
module can be bypassed by bit
SYBE
of the
RxRSVitAct
register. When set, the
SYBE
bit enables the
synchronization between De–Puncturing and Viterbi blocks; when cleared, the
Synchro–Bit
module still maintains the
SBF generation in order to allow other blocks to work; in this case the De–Puncturing rate is fixed (Rate = 1/2, no phase
ambiguity).
4.1.2. The Synchro–Frame module
Starting on successful
Synchro–Bit
process completion, the
Synchro_Frame
process waits for the frame
synchronization word (47h) or the transport packet one (B8h) by default. The sync words search duration is limited
by a timeout value defined through the
RxSyncWCtl
register
TOV
bits and
RxVitSyncCompWord
register
SCW
bits. An
unsuccessful sync words search produces an interrupt and sets the
RxVitRSInt0
register
TiO
flag.
Whenever either sync word or bitwise inverted sync word is found, a counter is incremented and compared to the
number of consecutive sync words at the expected position required to get synchronized (RxSyncWCtl register
SY2/SY1/SY0
bits). The
Synchro–Frame
process remains in the sync word waiting loop until the expected number of
consecutive sync words is reached, then the
Synchro–Frame
block sets the
RxVitStatus
register
LCK
bit
(Synchro–Frame locked).
The default sync word value is 47h but it may be changed to any value through the
RxSyncWord
register. The sync
condition may take into account the bitwise inverted sync word search or not (RxVitSyncCompWord register
CENA
bit).
The bitwise inverted sync word occurs every 8 frames by default but this value may be changed from 1 to 15
(RxVitSyncCompWord register
SCW3
to
SCW0
bits).
A maximum number of allowed mismatching bits can be defined when expecting the sync word (RxSyncWctl register
MSY
bits).
The
Synchro–Frame
process may restart under the following external conditions:
D
a general reset is applied to the device.
D
the
Synchro_Frame
module receives a restart signal from the
Synchro–Bit
block.
D
the bit synchronization is lost.
D
the Reed–Solomon decoder is out of sync (RxDeSyncWCtl register
DRSM
bit); this condition may be masked.
D
the descrambler module is out of sync (RxDeSyncWCtl register
DSCM
bit); this condition may be masked.
The
Synchro–Frame
module will lose sync again after lock, when the sync word is not found at the expected position
for a number of consecutive frames which is specified in
RxVitDeSyncWCtl
register
DSY[2:0].
The maximum number
of mismatching bits for a missed sync word is programmable (RxVitDeSyncWCtl register
MDS[1:0]
bits).
A loss of synchronization restarts a search of frame synchro. The Data processing of blocks placed after sync–frame
block is restarted as well.
The
Synchro–Frame
module can be bypassed by bit
SYE
of the
RxRSVitAct
register.
Rev. D
–
April 1999
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