INTEGRATED CIRCUITS
DATA SHEET
TZA3005H
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
Product specification
Supersedes data of 1997 Aug 05
File under Integrated Circuits, IC19
2000 Feb 17
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
FEATURES
•
Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12
(622.08 Mbits/s)
•
Supports reference clock frequencies of 19.44, 38.88,
51.84 and 77.76 MHz
•
Meets Bellcore, ANSI and ITU-T specifications
•
Meets ITU jitter specification typically to a factor of 2.5
•
Integral high-frequency PLL for clock generation
•
Interface to TTL logic
•
Low jitter PECL (Positive Emitter Coupled Logic)
interface
•
4 or 8-bit STM1/OC3 TTL data path
•
4 or 8-bit STM4/OC12 TTL data path
•
No external filter components required
•
QFP64 package
•
Diagnostic and line loopback modes
•
Lock detect
•
LOS (Loss of Signal) input
•
Low power (0.9 W typical)
•
Selectable frame detection and byte realignment
•
Loop timing
•
Forward and reverse clocking
•
Squelched clock operation
•
Self-biased PECL inputs to support AC coupling.
APPLICATIONS
•
SDH/SONET modules
•
SDH/SONET-based transmission systems
•
SDH/SONET test equipment
•
ATM (Asynchronous Transfer Mode) over SDH/SONET
•
Add drop multiplexers
•
Broadband cross-connects
•
Section repeaters
•
Fibre optic test equipment
•
Fibre optic terminators.
ORDERING INFORMATION
TYPE
NUMBER
TZA3005H
PACKAGE
NAME
QFP64
DESCRIPTION
plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14
×
14
×
2.7 mm
GENERAL DESCRIPTION
TZA3005H
The TZA3005H SDH/SONET transceiver chip is a fully
integrated serialization/deserialization STM1/OC3
(155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s)
interface device. It performs all necessary serial-to-parallel
and parallel-to-serial functions in accordance with
SDH/SONET transmission standards. It is suitable for
SONET-based applications and can be used in
conjunction with the data and clock recovery unit
(TZA3004), optical front-end (TZA3023 with TZA3034/44)
and a laser driver (TZA3001). A typical network application
is shown in Fig.10.
A high-frequency phase-locked loop is used for on-chip
clock synthesis, which allows a slower external transmit
reference clock to be used. A reference clock of 19.44,
38.88, 51.84 or 77.76 MHz can be used to support existing
system clocking schemes. The TZA3005H also performs
SDH/SONET frame detection.
The low jitter PECL interface ensures that Bellcore, ANSI,
and ITU-T bit-error rate requirements are satisfied.
The TZA3005H is supplied in a compact QFP64 package.
VERSION
SOT393-1
2000 Feb 17
2
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
BLOCK DIAGRAM
TZA3005H
handbook, full pagewidth
LLEN
TXPD0 to
TXPD7
TXPCLK
31
53 to 60
61
8
TRANSMITTER
D
2
17, 18
TXSD and
TXSDQ
8:1 OR 4:1
PARALLEL TO SERIAL
MRST
TEST1
TEST2
TEST3
BUSWIDTH
48
10
11
13
30
RF
SWITCH
BOX
2
21, 20
TXSCLK and
TXSCLKQ
(1)
TZA3005H
REFSEL0 and
REFSEL1
MODE
REFCLK and
REFCLKQ
SDTTL
SDPECL
OOF
DLEN
RXSD and
RXSDQ
RXSCLK and
RXSCLKQ
3, 4
49
15, 14
22
23
33
32
24, 25
27, 28
2
CLOCK
SYNTHESIZER
2
CLOCK
DIVIDER
BY 4 OR BY 8
62
63
64
8
on-chip capacitor
2
1:8 OR 1:4
SERIAL TO PARALLEL
47
35
36, 37, 39, 40,
41, 43 to 45
SYNCLKDIV
LOCKDET
19MHZO
RXPD0 to
RXPD7
RXPCLK
FP
2
2
D
FRAME HEADER DETECT
52
51
VCC(TXCORE)
GNDTXCORE
MGS975
RECEIVER
1
VCC(SYNOUT)
GNDSYNOUT
DGNDSYN
AGNDSYN
2
5
8, 9
6
7
12
GND
16
19
26
29
38, 46 34, 42
GNDRXOUT
VCC(RXOUT)
GNDRXCORE
VCC(RXCORE)
VCCD(SYN)
VCCA(SYN)
GNDTXOUT
VCC(TXOUT)
(1) Dashed lines represent normal operation mode.
Fig.1 Block diagram.
2000 Feb 17
3
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
PINNING
SYMBOL
V
CC(SYNOUT)
GND
SYNOUT
REFSEL0
REFSEL1
DGND
SYN
V
CCD(SYN)
V
CCA(SYN)
AGND
SYN
AGND
SYN
TEST1
TEST2
GND
TEST3
REFCLKQ
REFCLK
V
CC(TXOUT)
TXSD
TXSDQ
GND
TXOUT
TXSCLKQ
TXSCLK
SDTTL
SDPECL
RXSD
RXSDQ
V
CC(RXCORE)
RXSCLK
RXSCLKQ
GND
RXCORE
BUSWIDTH
LLEN
DLEN
OOF
GND
RXOUT
FP
RXPD0
RXPD1
V
CC(RXOUT)
RXPD2
RXPD3
2000 Feb 17
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TYPE
(1)
S
G
I
I
G
S
S
G
G
I
I
G
I
I
I
S
O
O
G
O
O
I
I
I
I
S
I
I
G
I
I
I
I
G
O
O
O
S
O
O
ground (synthesizer output)
reference clock select input 0
reference clock select input 1
digital ground (synthesizer)
digital supply voltage (synthesizer)
analog supply voltage (synthesizer)
analog ground (synthesizer)
analog ground (synthesizer)
test and control input
test and control input
ground
test and control input
inverted reference clock input
reference clock input
supply voltage (transmitter output)
serial data output
inverted serial data output
ground (transmitter output)
inverted serial clock output
serial clock output
TTL signal detect input
PECL signal detect input
serial data input
inverted serial data input
supply voltage (receiver core)
serial clock input
inverted serial clock input
ground (receiver core)
4/8 bus width select input
line loopback enable input (active LOW)
diagnostic loopback enable input (active LOW)
out-of-frame enable input
ground (receiver output)
frame pulse output
parallel data output 0
parallel data output 1
supply voltage (receiver output)
parallel data output 2
parallel data output 3
4
DESCRIPTION
supply voltage (synthesizer output)
TZA3005H
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
SYMBOL
RXPD4
GND
RXOUT
RXPD5
RXPD6
RXPD7
V
CC(RXOUT)
RXPCLK
MRST
MODE
ALTPIN
GND
TXCORE
V
CC(TXCORE)
TXPD0
TXPD1
TXPD2
TXPD3
TXPD4
TXPD5
TXPD6
TXPD7
TXPCLK
SYNCLKDIV
LOCKDET
19MHZO
Note
1. Pin type abbreviations: O = Output, I = Input, S = Supply, G = Ground.
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TYPE
(1)
O
G
O
O
O
S
O
I
I
I
G
S
I
I
I
I
I
I
I
I
I
O
O
O
parallel data output 4
ground (receiver output)
parallel data output 5
parallel data output 6
parallel data output 7
supply voltage (receiver output)
receive parallel clock output
master reset (active LOW)
serial data rate select STM1/STM4
test and control input
ground (transmitter core)
supply voltage (transmitter core)
parallel data input 0
parallel data input 1
parallel data input 2
parallel data input 3
parallel data input 4
parallel data input 5
parallel data input 6
parallel data input 7
transmit parallel clock input
transmit byte/nibble clock output (synchronous)
lock detect output
19 MHz reference clock output
DESCRIPTION
TZA3005H
2000 Feb 17
5
