Features
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Minimal External Circuitry Requirements, No RF Components on the PC Board Except
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Matching to the Receiver Antenna
High Sensitivity, Especially at Low Data Rates
Sensitivity Reduction Possible Even While Receiving
Fully Integrated VCO
Low Power Consumption Due to Configurable Self Polling with a Programmable Time
Frame Check
Supply Voltage 4.5 V to 5.5 V
Operating Temperature Range -40°C to 105°C
Single-ended RF Input for Easy Adaptation to
l/4
Antenna or Printed Antenna on PCB
Low-cost Solution Due to High Integration Level
ESD Protection According to MIL-STD 883 (4KV HBM) Except Pin POUT (2KV HBM)
High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW
Front-end Filter
– Up to 40 dB is Thereby Achievable with Newer SAWs.
Programmable Output Port for Sensitivity Selection or for Controlling External
Periphery
Communication to the Microcontroller Possible via a Single, Bi-directional Data Line
Power Management (Polling) is also Possible by Means of a Separate Pin via the
Microcontroller
2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)
UHF ASK
Receiver IC
U3741BM
Description
The U3741BM is a multi-chip PLL receiver device supplied in an SO20 package. It has
been specially developed for the demands of RF low-cost data transmission systems
with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in
Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL
RF transmitter U2741B. Its main applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in the frequency receiving
range of f
0
= 300 MHz to 450 MHz for ASK or FSK data transmission. All the state-
ments made below refer to 433.92-MHz and 315-MHz applications.
Rev. 4662A–RKE–06/03
1
System Block Diagram
UHF ASK
Remote control transmitter
UHF ASK
Remote control receiver
1 Li cell
U2741B
U3741BM
Demod.
Control
1...3
mC
Keys
Encoder
M44Cx9x
XTO
PLL
IF Amp
Antenna Antenna
VCO
PLL
XTO
Power
amp.
LNA
VCO
Pin Configuration
Figure 1.
Pinning SO20
SENS
FSK/ASK
CDEM
AVCC
AGND
DGND
MIXVCC
LNAGND
LNA_IN
NC
1
20
DATA
ENABLE
TEST
POUT
MODE
DVCC
XTO
LFGND
LF
LFVCC
2
19
3
18
4
17
5
16
U3741BM
6
15
7
14
8
13
9
12
10
11
2
U3741BM
4662A–RKE–06/03
U3741BM
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
SENS
FSK/ASK
CDEM
AVCC
AGND
DGND
MIXVCC
LNAGND
LNA_IN
NC
LFVCC
LF
LFGND
XTO
DVCC
MODE
POUT
TEST
ENABLE
DATA
Function
Sensitivity-control resistor
Selecting FSK/ASK. Low: FSK, High: ASK
Lower cut-off frequency data filter
Analog power supply
Analog ground
Digital ground
Power supply mixer
High-frequency ground LNA and mixer
RF input
Not connected
Power supply VCO
Loop filter
Ground VCO
Crystal oscillator
Digital power supply
Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA). High: 6.76438 (Europe)
Programmable output port
Test pin, during operation at GND
Enables the polling mode
Low: polling mode off (sleep mode)
H: polling mode on (active mode)
Data output/configuration input
3
4662A–RKE–06/03
Block Diagram
V
S
FSK/ASK
CDEM
AVCC
SENS
IF Amp
Sensitivity
reduction
Polling circuit
and
control logic
FSK/ASK-
Demodulator
and data filter
RSSI
DEMOD_OUT
50 kW
DATA
Limiter out
ENABLE
TEST
POUT
MODE
FE
CLK
DVCC
AGND
DGND
4
th
Order
MIXVCC
LPF
3 MHz
Standby logic
LFGND
LNAGND
IF Amp
LFVCC
LPF
3 MHz
VCO
XTO
XTO
f
LNA_IN
LNA
¸
64
LF
4
U3741BM
4662A–RKE–06/03
U3741BM
RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input
signal into a 1-MHz IF signal. According to the block diagram, the front end consists of
an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency f
XTO
. The VCO (voltage-controlled
oscillator) generates the drive voltage frequency f
LO
for the mixer. f
LO
is dependent on
the voltage at pin LF. f
LO
is divided by a factor of 64. The divided frequency is compared
to f
XTO
by the phase frequency detector. The current output of the phase frequency
detector is connected to a passive loop filter and thereby generates the control voltage
V
LF
for the VCO. By means of that configuration, V
LF
is controlled in a way that f
LO
/64 is
equal to f
XTO
. If f
LO
is determined, f
XTO
can be calculated using the following formula:
f
LO
f
XTO
= -------
-
64
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys-
tal. According to Figure 2, the crystal should be connected to GND via a capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of f
XTO
and
hereby of f
LO
. When designing the system in terms of receiving bandwidth, the accuracy
of the crystal and XTO must be considered.
Figure 2.
PLL Peripherals
V
S
DVCC
C
L
XTO
LFGND
LF
V
S
R1
C9
C10
R1 = 820
W
C9 = 4.7 nF
C10 = 1 nF
LFVCC
The passive loop filter connected to Pin LF is designed for a loop bandwidth of
BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of
the LO. Figure 2 shows the appropriate loop filter components to achieve the desired
loop bandwidth. If the filter components are changed for any reason, please note that
the maximum capacitive load at Pin LF is limited. If the capacitive load is exceeded, a bit
check may no longer be possible since f
LO
cannot settle in time before the bit check
starts to evaluate the incoming data stream. Therefore, self polling also does not work in
that case.
f
LO
is determined by the RF input frequency f
RF
and the IF frequency f
IF
using the follow-
ing formula:
5
4662A–RKE–06/03
