UNISONIC TECHNOLOGIES CO., LTD
UCD4071
QUAD 2-INPUT OR
BUFFERED B SERIES GATE
DESCRIPTION
The
UTC UCD4071
contains four independent 2-input OR gates
and they perform the function
Y=A+B
in positive logic.
CMOS IC
FEATURES
* 5V-10V-15V Parametric Ratings
* Quad 2-Input OR Gate
* Symmetrical Output Characteristics
* Maximum Input Current of 1uA at 15V Over Full Package Temper-
ature
* Low Power TTL:
Fan Out of 2 Driving 74L or 1 Driving 74LS Compatibility
SOP-14
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
UCD4071L-S14-R
UCD4071G-S14-R
Package
SOP-14
Packing
Tape Reel
www.unisonic.com.tw
Copyright © 2012 Unisonic Technologies Co., Ltd
1 of 5
QW-R502-520.b
UCD4071
PIN CONFIGURATION
CMOS IC
FUNCTION TABLE
(each gate)
INPUT(A)
H
H
L
L
INPUT(B)
H
L
H
L
OUTPUT(Y)
H
H
H
L
LOGIC DIAGRAM
(positive logic)
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QW-R502-520.b
UCD4071
ABSOLUTE MAXIMUM RATING
(T
A
=25°С, unless otherwise specified)
PARAMETER
CMOS IC
SYMBOL
RATINGS
UNIT
Supply Voltage
VDD
-0.5 ~ 18
V
Input Voltage
V(nA,nB)
-0.5 ~ VDD +0.5
V
Output Voltage
V(nY)
-0.5 ~ VDD +0.5
V
Storage Temperature
T
STG
-65 ~ + 150
°С
Lead Temperature(Soldering,10s)
T
L
260
°С
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Operating Temprature
SYMBOL
VDD
T
OP
RATINGS
3
~
15
-40 ~ +125
UNIT
V
°С
ELECTRICAL CHARACTERISTICS
(T
A
=25°С, unless otherwise specified)
TEST CONDITIONS
VDD= 5V, VO=0.5V
High-Level Input Voltage
V
IH
VDD= 10V, VO=1.0V
VDD= 15V, VO=1.5V
VDD= 5V, VO=4.5V
Low-Level Input Voltage
V
IL
VDD= 10V, VO=9.0V
VDD= 15V, VO=13.5V
VDD= 5V, I
OH
=1µA
High-Level Output Voltage
V
OH
VDD= 10V, I
OH
=1µA
VDD= 15V, I
OH
=1µA
VDD= 5V, I
OL
=1µA
Low-Level Output Voltage
V
OL
VDD= 10V, I
OL
=1µA
VDD= 15V, I
OL
=1µA
VDD= 5V, VO=4.6V
High-Level Output Current
I
OH
VDD= 10V, VO=9.5V
(NOTE)
VDD= 15V, VO=13.5V
VDD= 5V, VO=0.4V
Low-Level Output Current
I
OL
VDD= 10V, VO=0.5V
(NOTE)
VDD= 15V, VO=1.5V
Input Leakage Current
I
I(LEAK)
VDD= 15V ,V
IN
= VDD or GND
VDD= 5V, V
IN
= VDD or VSS, I
OUT
= 0
Quiescent Supply Current
I
Q
VDD= 10V, V
IN
= VDD or VSS, I
OUT
= 0
VDD= 15V, V
IN
= VDD or VSS, I
OUT
= 0
Note: I
OL
and I
OH
are tested one output at a time
PARAMETER
SYMBOL
MIN
3.5
7.0
11.0
TYP
3
6
9
2
4
6
5
10
15
0
0
0
-0.88
-2.25
-8.8
0.88
2.25
8.8
0.004
0.005
0.006
MAX
UNIT
V
1.5
3.0
4.0
V
4.95
9.95
14.95
V
0.05
0.05
0.05
V
-0.51
-1.3
-3.4
0.51
1.3
3.4
mA
0.1
0.25
0.5
1.0
µA
µA
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3 of 5
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UCD4071
PARAMETER
SYMBOL
t
PLH
Propagation delay from
Input(A or B) to Output(Y)
t
PHL
t
TLH
t
THL
TEST CONDITIONS
VDD=5V, C
L
=50pF, R
L
=200kΩ
VDD=10V, C
L
=50pF, R
L
=200kΩ
VDD=15V, C
L
=50pF, R
L
=200kΩ
VDD=5V, C
L
=50pF, R
L
=200kΩ
VDD=10V, C
L
=50pF, R
L
=200kΩ
VDD=15V, C
L
=50pF, R
L
=200kΩ
VDD=5V, C
L
=50pF, R
L
=200kΩ
VDD=10V, C
L
=50pF, R
L
=200kΩ
VDD=15V, C
L
=50pF, R
L
=200kΩ
MIN
TYP
90
40
30
100
40
30
90
50
40
CMOS IC
SWITCHING CHARACTERISTICS
(T
A
=25°С, Input: t
R
=t
F
=20ns, unless otherwise specified)
MAX
250
100
70
250
100
70
200
100
80
UNIT
ns
Transition Time
ns
OPERATING CHARACTERISTICS
(T
A
=25°С, unless otherwise specified)
PARAMETER
Average Input Capacitance
Power Dissipation Capacitance
SYMBOL
Cin
Cpd
TEST CONDITIONS
Any Input
Any Gate
MIN
TYP
5
18
MAX
7.5
UNIT
pF
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4 of 5
QW-R502-520.b
UCD4071
TEST CIRCUIT AND WAVEFORMS
Output
C
L
50pF
R
L
200kΩ
CMOS IC
Definitions for test circuit
V
I
V
CC
50%
50%
t
PLH
Vo
50%
t
PHL
50%
0V
V
OH
V
OL
Propagation Delay Times
Note: CL includes probe and jig capacitance.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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www.unisonic.com.tw
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FPGA/CPLD
