µClamp
TM
1-Line ESD Protection
PROTECTION PRODUCTS - MicroClamp
TM
Description
The
µClamp
TM
series of TVS arrays are designed to protect
sensitive electronics from damage or latch-up due to ESD.
It is designed to replace multilayer varistors (MLVs) in por-
table applications such as cell phones, notebook comput-
ers, and PDAs. It features large cross-sectional area junc-
tions for conducting high transient currents. It offers
superior electrical characteristics such as lower clamp-
ing voltage and no device degradation when compared
to MLVs. They offer desirable characteristics for board
level protection including fast response time, low oper-
ating and clamping voltage, and no device degradation.
The µClamp
TM
1201H is in a 2-pin, RoHS compliant,
SOD-523 package. The leads are finished with lead-
free matte tin. Each device will protect one line oper-
ating at 12 volts. It gives the designer the flexibility to
protect single lines in applications where arrays are not
practical. They may be used to meet the ESD immunity
requirements of IEC 61000-4-2, Level 4 (15kV air, 8kV
contact discharge). The combination of small size and
high ESD surge capability makes them ideal for use in
portable applications such as cellular phones, digital
cameras, and MP3 players.
uClamp1201H
Features
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (tp = 5/50ns)
Cable Discharge Event (CDE)
Ultra-small SOD-523 package (1.7 x 0.9 x 0.7mm)
Protects one I/O or power line
Low clamping voltage
Working voltage: 12V
Low leakage current
Solid-state silicon-avalanche technology
Mechanical Characteristics
EIAJ SOD-523 package
Molding compound flammability rating: UL 94V-0
Marking: Marking code, cathode band
Packaging: Tape and Reel per EIA 481
Lead Finish: Matte tin
RoHS Compliant
Applications
Cellular Handsets & Accessories
Personal Digital Assistants (PDAs)
Notebooks & Handhelds
Portable Instrumentation
Digital Cameras
Peripherals
MP3 Players
Dimensions
1.70
1.30
0.9
Schematic & PIN Configuration
0.35
0.70
Maximum Dimensions (mm)
Revision 03/08/2005
1
SOD-523 (Top View)
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uClamp1201H
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (tp = 8/20µs)
Maximum Peak Pulse Current (tp = 8/20µs)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
p k
I
p p
V
PP
T
L
T
J
T
STG
Value
200
8
+/- 20
+/- 15
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
Amps
kV
°C
°C
°C
Electrical Characteristics (T=25
o
C)
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Forward Voltage
Clamp ing Voltage
Clamp ing Voltage
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
F
V
C
V
C
C
j
I
t
= 1mA
V
RWM
= 12V, T=25°C
I
F
= 10mA
I
PP
= 1A, t
p
= 8/20µs
I
PP
= 8A, t
p
= 8/20µs
V
R
= 0V, f = 1MHz
0.8
19
25
60
13.3
1
Conditions
Minimum
Typical
Maximum
12
Units
V
V
µA
V
V
V
pF
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uClamp1201H
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Power Derating Curve
110
100
90
% of Rated Power or I
PP
80
70
60
50
40
30
20
10
0
Peak Pulse Power - P
PP
(kW)
1
0.1
0.01
0.1
1
10
Pulse Duration - tp (us)
100
1000
0
25
50
75
100
o
125
150
Ambient Temperature - T
A
( C)
Clamping Voltage vs. Peak Pulse Current
25
3.5
3
Forward Voltage - V
F
(V)
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
7
Peak Pulse Current - I
PP
(A)
8
9
10
0
Forward Voltage vs. Forward Current
Clamping Voltage - V
C
(V)
20
15
10
Waveform
Parameters:
tr = 8µs
td = 20µs
5
Waveform
Parameters:
tr = 8µs
td = 20µs
0
1
2
3
4
5
Forward Current - I
F
(A)
6
7
8
Junction Capacitance vs. Reverse Voltage
1.1
1
0.9
Normalized Capacitance
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
Reverse Voltage - V
R
(V)
4
5
f = 1 MHz
ESD Clamping
(8kV Contact per IEC 61000-4-2)
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uClamp1201H
PROTECTION PRODUCTS
Applications Information
Device Connection Options
These TVS diodes are designed to protect one data,
I/O, or power supply line. The device is unidirectional
and may be used on lines where the signal polarity is
above ground. The cathode band should be placed
towards the line that is to be protected.
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
Circuit Diagram
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uClamp1201H
PROTECTION PRODUCTS
Applications Information - Spice Model
0.5 nH
Figure 1 - uClamp1201H Spice Model
Table 1 - uClamp1201H Spice Parameters
Parameter
IS
BV
VJ
RS
IB V
CJO
TT
M
N
EG
Unit
Amp
Volt
Volt
Ohm
A mp
Farad
sec
--
--
eV
D1 (T VS)
1.48E-14
15.33
0.723
0.772
1.0E-3
52E-12
2.541E-9
0.268
1.1
1.11
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