INTEGRATED CIRCUITS
DATA SHEET
UDA1351TS
96 kHz IEC 958 audio DAC
Product specification
Supersedes data of 2000 Mar 28
File under Integrated Circuits, IC01
2001 Feb 05
Philips Semiconductors
Product specification
96 kHz IEC 958 audio DAC
CONTENTS
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.5.1
8.5.2
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.6.9
FEATURES
General
Control
IEC 958 input
Digital sound processing and DAC
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Clock regeneration and lock detection
Mute
Auto mute
Data path
IEC 958 input
Audio feature processor
Interpolator
Noise shaper
The Filter Stream DAC (FSDAC)
Control
Static pin control mode
L3 control mode
L3 interface
General
Device addressing
Register addressing
Data write mode
Data read mode
initialization string
Overview of L3 interface registers
Writable registers
Readable registers
16
17
15.2
15.3
15.4
15.5
9
10
11
12
13
14
15
15.1
LIMITING VALUES
UDA1351TS
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DEFINITIONS
LIFE SUPPORT APPLICATIONS
2001 Feb 05
2
Philips Semiconductors
Product specification
96 kHz IEC 958 audio DAC
1
1.1
FEATURES
General
UDA1351TS
•
2.7 to 3.6 V power supply
•
Integrated digital filter and Digital-to-Analog Converter
(DAC)
•
Master-mode data output and input interface for off-chip
sound processing
•
256f
s
system clock output
•
20-bit data path in interpolator
•
High performance
•
No analog post filtering required for DAC
•
Support sampling frequencies from 28 kHz up to
100 kHz
•
The UDA1351TS is fully pin and function compatible
with the UDA1350ATS.
1.2
Control
3
GENERAL DESCRIPTION
Available in two versions:
•
UDA1351TS:
– only IEC 958 input to DAC in SSOP28 package.
•
UDA1351H:
– full featured version in QFP44 package.
The UDA1351TS is a single chip IEC 958 audio decoder
with an integrated stereo DAC employing bitstream
conversion techniques.
A lock indication signal is available on pin LOCK,
indicating that the IEC 958 decoder is locked. This pin is
also used to indicate whether PCM data is applied to the
input or not. When non-PCM data is detected, the device
indicates out-of-lock.
By default, the DAC output and the data output interface
are muted when the decoder is out-of-lock. However, this
setting can be overruled in the L3 control mode.
Controlled either by means of static pins or via the
L3 microcontroller interface.
1.3
IEC 958 input
2
APPLICATIONS
Digital audio systems.
•
On-chip amplifier for converting IEC 958 input to CMOS
levels
•
Lock indication signal available on pin LOCK
•
Lock indication signal combined on-chip with the Pulse
Code Modulation (PCM) status bit; when non-PCM is
detected, pin LOCK indicates out-of-lock
•
Key channel-status bits available via L3 interface (lock,
pre-emphasis, audio sample frequency, two channel
PCM indication and clock accuracy).
1.4
Digital sound processing and DAC
•
Automatic de-emphasis when using IEC 958 input with
32.0, 44.1 and 48.0 kHz audio sample frequencies
•
Soft mute by means of a cosine roll-off circuit selectable
via pin MUTE or the L3 interface
•
dB linear volume control with 1 dB steps from 0 dB to
−60
dB and
−∞
dB
•
Bass boost and treble control in L3 control mode
•
Interpolating filter (f
s
to 128f
s
) by means of a cascade of
a recursive filter and a FIR filter
•
Third order noise shaper operating at 128f
s
generates
the bitstream for the DAC
•
Filter Stream DAC (FSDAC).
2001 Feb 05
3
Philips Semiconductors
Product specification
96 kHz IEC 958 audio DAC
4
QUICK REFERENCE DATA
SYMBOL
Supplies
V
DDD
V
DDA
I
DDA(DAC)
I
DDA(PLL)
I
DDD(C)
I
DDD
P
digital supply voltage
analog supply voltage
analog supply current of DAC
analog supply current of PLL
digital supply current of core
digital supply current
power-on
Power-down
at 48 kHz
at 96 kHz
at 48 kHz
at 96 kHz
at 48 kHz
at 96 kHz
power consumption at 48 kHz DAC in playback mode
DAC in Power-down mode
power consumption at 96 kHz DAC in playback mode
DAC in Power-down mode
General
t
rst
T
amb
V
o(rms)
reset active time
ambient temperature
−
−40
note 1
f
i
= 1.0 kHz tone at 48 kHz
at 0 dB
at
−40
dB; A-weighted
f
i
= 1.0 kHz tone at 96 kHz
at 0 dB
at
−40
dB; A-weighted
S/N
α
cs
∆V
o
Note
1. The output voltage of the DAC is proportional to the DAC power supply voltage.
5
ORDERING INFORMATION
TYPE
NUMBER
UDA1351TS
PACKAGE
NAME
SSOP28
DESCRIPTION
plastic shrink small outline package; 28 leads; body width 5.3 mm
−
−
−
−
−
2.7
2.7
−
−
−
−
−
−
−
−
−
−
−
−
PARAMETER
CONDITIONS
MIN.
UDA1351TS
TYP.
MAX.
UNIT
3.0
3.0
8.0
750
0.7
1.0
16.0
24.5
2.0
3.0
80
58
109
87
3.6
3.6
−
−
−
−
−
−
−
−
−
−
−
−
−
+85
−
−85
−55
−80
−52
−
−
−
0.4
V
V
mA
µA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
µs
°C
mV
dB
dB
dB
dB
dB
dB
dB
dB
250
−
900
−90
−60
−85
−57
100
100
96
0.1
Digital-to-analog converter
output voltage (RMS value)
(THD + N)/S total harmonic
distortion-plus-noise to signal
ratio
signal-to-noise ratio at 48 kHz f
i
= 1.0 kHz tone; code = 0; A-weighted 95
signal-to-noise ratio at 96 kHz f
i
= 1.0 kHz tone; code = 0; A-weighted 95
channel separation
unbalance of output voltages
f
i
= 1.0 kHz tone
f
i
= 1.0 kHz tone
−
−
VERSION
SOT341-1
2001 Feb 05
4
Philips Semiconductors
Product specification
96 kHz IEC 958 audio DAC
6
BLOCK DIAGRAM
UDA1351TS
handbook, full pagewidth
TEST1
TEST3
TEST4
28
25
VSSA
VDDA
21
22
VDDA(DAC)
VOUTL
15
Vref
VOUTR
19
17
TEST2
4
18
VSSA(DAC)
14
20
VDDA(PLL)
VSSA(PLL)
24
23
CLOCK
AND
TIMING CIRCUIT
DAC
DAC
NOISE SHAPER
VDDD(C)
6
UDA1351TS
INTERPOLATOR
L3MODE
L3CLOCK
L3DATA
SELSTATIC
10
9
8
26
SLICER
L3
INTERFACE
AUDIO FEATURE PROCESSOR
11
MUTE
SPDIF
VDDD
VSSD
VSSD(C)
13
3
7
12
1, 2, 27
n.c.
IEC 958
DECODER
5
RESET
16
MGU032
LOCK
Fig.1 Block diagram.
2001 Feb 05
5
