Evaluation Board User Guide
UG-486
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
iCoupler
EVAL-ADuM5211EBZ,
150 mW
isoPower
Evaluation Board
FEATURES
isoPower
integrated, isolated dc-to-dc converter
Regulated 3.15 V or 5.25 V output
Up to 150 mW output power
20-lead SSOP package with 5 mm creepage
High temperature operation: 105°C
High common-mode transient immunity: >25 kV/µs
GENERAL DESCRIPTION
The
EVAL-ADuM5211EBZ
supports the
ADuM5210/
ADuM5211/ADuM5212
and
ADuM6210/ADuM6211/
ADuM6212
150 mW isolated power modules. It provides
a JEDEC standard SSOP20 pad layout as well as support for
setting the desired output voltage, setting enable control and
providing multiple positions for on-board loads and bypass
capacitors.
isoPower
devices employ high frequency, high power switching
circuits to enable power transfer across chip scale, air core
transformers. The evaluation board includes EMI mitigation
recommendations from the
AN-0971 Application Note.
With
the included techniques, this PCB and power module is capable
of meeting the requirements of CISPER22 Class A or Class B
depending on the voltage and load range.
Complete specifications for the
ADuM5210/ ADuM5211/
ADuM5212
and
ADuM6210/ADuM6211/ADuM6212
are
provided in the
ADuM5210/ADuM5211/ADuM5212
and
ADuM6210/ADuM6211/ADuM6212
data sheets, available
from Analog Devices, Inc., and should be consulted in conjunc-
tion with this user guide when using the evaluation board.
SUPPORTED
iCoupler®
MODELS
ADuM5210
ADuM5211
ADuM5212
ADuM6210
ADuM6211
ADuM6212
EVALUATION BOARD
Figure 1.
EVAL-ADuM5211EBZ
Evaluation Board
See the last page for an important warning and disclaimers.
Rev. 0 | Page 1 of 8
11070-001
UG-486
TABLE OF CONTENTS
Features .............................................................................................. 1
Supported
iCoupler®
Models........................................................... 1
General Description ......................................................................... 1
Evaluation Board .............................................................................. 1
Revision History ............................................................................... 2
PCB Evaluation Goals .................................................................. 3
Connectors .................................................................................... 3
Part Configuration Structures .................................................... 3
Bypass on the PCB........................................................................ 3
Evaluation Board User Guide
Provision for Loading ...................................................................3
Data I/O ..........................................................................................4
EMI Mitigation ..............................................................................4
High Voltage Testing .....................................................................4
Evaluation Board Schematics and Artwork ...................................6
Ordering Information .......................................................................8
Bill of Materials ..............................................................................8
REVISION HISTORY
1/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
Evaluation Board User Guide
PCB EVALUATION GOALS
This board is intended to achieve three goals.
•
It will allow a user of the
ADuM5210/ADuM5211/
ADuM5212
or
ADuM6210/ADuM6211/ADuM6212
to
exercise the functional capabilities of the power converter.
These include evaluation of bypass, loading, power supply
enable/disable control, and setting the adjustable output
voltage level.
All data channel configurations of the entire family can be
exercised.
This evaluation board demonstrates the EMI mitigation
techniques required to make a low emissions design as set
out in the
AN-0971 Application Note.
UG-486
PART CONFIGURATION STRUCTURES
The
ADuM5210/ADuM5211/ADuM5212
and
ADuM6210/
ADuM6211/ADuM6212
have pins that must have set inputs for
the IC to operate properly. The evaluation board allows all parts
a full range of configuration options. On the primary side, the
PDIS pin must either be tied low to enable the converter, or
pulled high to disable the output power and put the part in a
standby state. Connector P3A allows a jumper to be placed
between Pin 1 and Pin 2 to disable the converter, or between
Pin 2 and Pin 3 to enable the converter. The header can be
removed if an external logic source controls the disable function
and the signal can be fed directly into Position 2 of the header.
Control of the V
ISO
voltage is accomplished through a voltage
divider that’s center node is attached to the V
SEL
pin as shown
in Figure 3. There are two options for setting the output voltage
supported on this evaluation board. A 20 kΩ potentiometer is
installed at R1A in series with a 16.5 kΩ resistor at Position R16A
making a variable resistance to V
ISO
of 16.5 kΩ to 36 kΩ. A
10 kΩ resistor to ground at Position R14A forms the lower leg
of the voltage divider. This will give a range of adjustment of
V
ISO
< 3.3 V to > 5.0 V.
Alternatively, if a fixed output voltage is desired, R16A can be
removed and a resistor can be installed in R13A that combined
with the existing 10 kΩ resistance in R14A will form a fixed
voltage divider to set V
ISO
to a single voltage. Refer to the
ADuM5210/ADuM5211/ADuM5212
and
ADuM6210/
ADuM6211/ADuM6212
data sheets for a selection of
resistor values.
•
•
The
ADuM5210/ADuM5211/ADuM5212
and
ADuM6210/
ADuM6211/ADuM6212
have a pin layout that is compatible
with the
ADuM5010
and
ADuM6010.
These two additional
devices do not include data channels and consist of the
isoPower
module only. One PCB design supports all four
families of parts. Many of the structures on the PCB that
support the digital channels are not used for the
ADuM5010
and
ADuM6010
version of the PCB.
CONNECTORS
This evaluation system is used to examine a variety of different
aspects of performance. Connections to power and instrumen-
tation are critical to performing accurate measurements without
creating artificial ringing, reflections, ripple, and EMI.
Two types of interconnect are provided: SMA edge connectors
and through-hole signal ground pairs. Between these two
options, both temporary and permanent connections to the
board can easily be made. When coax connections are desired,
SMA connectors are available for the V
DDP
power input and V
ISO
output as well as all four data I/O pins. These connectors were
chosen because they are low profile and provide excellent
mechanical connections to the PCB. Most lab equipment is
geared toward use of BNC connectors, so adaptors will be
required to use the on board connectors.
Power can be directly wired to the PCB via the P6A and P7A
through-hole connectors. These provide a power ground pair
with the power on the Pin 1 hole. These through holes are
on 200mil centers, which match the pin spacing required
for Tektronix active probes. These positions can be used for
scope test points or direct wiring of power and ground.
In many cases, the data inputs will be derived from function
generators through 50 Ω coax cables. The PCB includes
positions to install termination resistors to ground near
each connector. Two surface-mount pads are provided so
that two 100 Ω resistors can be placed in parallel to create a
50 Ω termination with sufficient power dissipation capability
to support a 5 V data stream.
BYPASS ON THE PCB
Several positions and structures are provided to allow optimum
bypass of the evaluation board. Provisions have been made for
optional surface-mount bulk capacitors to be installed near the
power connectors to compensate for long cables to the power
supply or external load. Parallel bypass capacitors are installed
near the
ADuM5210/ADuM5211/ADuM5212
or
ADuM6210/
ADuM6211/ADuM6212
consisting of a 0.1 µF and a 10 µF
capacitor for V
DDP
and V
ISO
. The 0.1 µF capacitors can be moved
to positions on the back side of the board if required.
The PCB also implements distributed capacitive bypass on the
primary side of the PCB. This consists of power and ground fills
on the top and bottom layers of the PCB on the V
DDP
side of
the board. This is one of the techniques discussed in the EMI
Mitigation section. It has the extra benefit of providing added
bypass on the primary side of the converter where the largest
currents flow as well as RF shielding.
PROVISION FOR LOADING
V
ISO
can be loaded three ways:
•
•
•
Rev. 0 | Page 3 of 8
An external load can be connected via the SMA connector.
A fixed resistor can be installed at R18A.
A surface-mount resistor can be installed at R15A.
UG-486
DATA I/O
There are two data I/O pins on each side of the board. For
example, examining Channel A on Side 1, Figure 3 shows the
following structures, starting from each I/O connector:
•
•
A position for a pull-down resistor or termination to be
installed in R2A and R4A.
A 0 Ω resistor at R6A connects the trace to the SMA
connector and termination. This allows extra trace length
and components to be removed when capacitance must
be controlled.
Two positions for connection of the trace to V
DDP
or GND.
R8A and C1A are available for a pull-up or pull-down
resistor or for a capacitive load when the I/O is an output.
There is the P1A test point, with a 200mil pitch. This is for
hard wiring inputs or installing a Tektronix active probe
header.
Position R10A allows interconnection of Channel A and
Channel B. Inputs on the same side can share a single off
board connection, or an output signal can be wrapped back
to an input.
Evaluation Board User Guide
Stitching Capacitance
Capacitance between the primary and secondary power
and ground planes is the most effective way to reduce high
frequency emissions from an
isoPower
device. Figure 2
shows how the inner layers of a PCB can create this stitching
capacitance by overlapping inner layer metal to create an
extremely low inductance capacitance. The green area
shows the active coupling area.
Edge Guarding
Providing guard rings laced together with vias on each layer of
the primary side reduces edge emissions from the PCB stack-up.
This addresses emissions due to differential currents flowing in
the ground planes from reaching the edge of the PCB where
they could radiate. Figure 4 shows the top layer guard ring and
the bottom layer ground fill as well as the regularly spaced vias
in the guard ring that creates a cage type structure to reflect
inter-plane emissions back into the PCB. Figure 5 shows the
top layer power fill along with its vias to the Layer 3 power
plane. This top layer power fill adds distributed capacitance
as well as shielding for the layer below.
•
•
•
The same set of structures is present on each channel, allowing
a wide range of tests to be conducted with minimum config-
uration.
HIGH VOLTAGE TESTING
This PCB is designed in line with 2500 V basic insulation
practices. High voltage testing beyond 2500 V is not recom-
mended. Appropriate care must be taken when using this
evaluation board at high voltages, and it should not be relied
on for safety functions because it has not been hi-pot tested
or certified for safety.
EMI MITIGATION
The PCB implements EMI mitigation techniques discussed
in the
AN-0971 Application Note
to demonstrate the recom-
mended board layout options for this device. These techniques
include stitching capacitance and edge guarding.
Rev. 0 | Page 4 of 8
Evaluation Board User Guide
LAYER 2 GROUND
LAYER 3 POWER
UG-486
OVERLAP
CREATING CAPACITANCE
Figure 2. Ground and Power Planes Creating Stitching Capacitance
Rev. 0 | Page 5 of 8
11070-003
ARM技术
