UJA1023
LIN-I/O slave
Rev. 5 — 17 August 2010
Product data sheet
1. General description
The UJA1023 is a stand-alone Local Interconnect Network (LIN) I/O slave that replaces
basic components commonly used in electronic control units for input and output handling.
The UJA1023 contains a LIN 2.0 controller, an integrated LIN transceiver which is
LIN 2.0 / SAE J2602 compliant and LIN 1.3 compatible, a 30 kΩ termination resistor
necessary for LIN-slaves, and eight I/O ports which are configurable via the LIN bus.
An automatic bit rate synchronization circuit adapts to any (master) bit rate between
1 kbit/s and 20 kbit/s. For this, an oscillator is integrated.
The LIN protocol will be handled autonomously and both Node Address (NAD) and LIN
frame Identifier (ID) programming will be done by a master request and an optional slave
response message in combination with a daisy chain or plug coding function.
The eight bidirectional I/O pins are configurable via LIN bus messages and can have the
following functions:
•
Input:
–
Standard input pin
–
Local wake-up
–
Edge capturing on falling, rising or both edges
–
Analog input pin
–
Switch matrix (in combination with output pins)
•
Output:
–
Standard output pin as high-side driver, low-side driver or push-pull driver
–
Cyclic sense mode for local wake-up
–
Pulse Width Modulation (PWM) mode; for example, for back light illumination
–
Switch matrix (in combination with input pins)
On entering a low-power mode it is possible to hold the last output state or to change over
to a user programmable output state. In case of a failure (e.g. LIN bus short to ground) the
output changes over to a user programmable limp home output state and the low-power
Limp home mode will be entered.
Due to the advanced low-power behavior the power consumption of the UJA1023 in
low-power mode is minimal.
NXP Semiconductors
UJA1023
LIN-I/O slave
2. Features and benefits
Automatic bit rate synchronization to any (master) bit rate between 1 kbit/s
and 20 kbit/s
Integrated LIN 2.0 / SAE J2602 transceiver (including 30 kΩ termination resistor)
Eight bidirectional I/O pins
4
×
2, 4
×
3, or 4
×
4 switch matrix to support reading and supplying a maximum
number of 16 switches
Outputs configurable as high-side and/or low-side driver and as cyclic or PWM driver
8-bit ADC
Advanced low-power behavior
On-chip oscillator
Node Address (NAD) configuration via daisy chain or plug coding
Inputs supporting local wake-up and edge capturing
Configurable Sleep mode
Limp home configuration in case of error conditions
Extremely low electromagnetic emission
High immunity against electromagnetic interference
Bus line protected in accordance with ISO 7637
Extended ambient temperature range (−40
°C
to +125
°C)
3. Quick reference data
Table 1.
V
BAT
I
BAT
Quick reference data
Conditions
all operating modes
LH sleep, Sleep and
Limp home mode;
V
BAT
= 8.1 V to 27 V
DC value
[3]
[1]
[2]
Symbol Parameter
supply voltage on pin BAT
supply current on pin BAT
Min
5.5
-
Typ
-
45
Max
27
65
Unit
V
μA
V
LIN
T
vj
V
ESD
[1]
[2]
[3]
voltage on pin LIN
virtual junction temperature
−27
−40
−8
-
-
-
+40
+150
+8
V
°C
kV
electrostatic discharge voltage
human body model;
on pins LIN, BAT, C1, C2 and C3 C = 100 pF; R = 1.5 kΩ
Valid for the UJA1023T/2R04/C; for the UJA1023T/2R04, V
BAT
= 6.5 V to 27 V.
All outputs turned off, LIN recessive, V
th1
selected.
Junction temperature in accordance with IEC60747-1. An alternative definition of T
vj
= T
amb
+ P
×
R
th(j-a)
,
where R
th(j-a)
is a fixed value to be used for calculating T
vj
. The rating for T
vj
limits the allowable
combinations of power dissipation (P) and ambient temperature (T
amb
).
UJA1023
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 17 August 2010
2 of 49
NXP Semiconductors
UJA1023
LIN-I/O slave
4. Ordering information
Table 2.
Ordering information
Package
Name
UJA1023T/2R04/C
[1]
UJA1023T/2R04
[1]
[1]
Type number
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
SOT109-1
SO16
SO16
V
BAT
= 5.5 V to 27 V for the UJA1023T/2R04/C; V
BAT
= 6.5 V to 27 V for the UJA1023T/2R04 (see
Table 32).
5. Block diagram
BAT
GND
3
5
VOLTAGE
REGULATOR
1
VIO
UJA1023
TERMINATION
LIN
4
ADC
LIN
TRANSCEIVER
AUTO
BIT RATE
DETECTION
OSCILLATOR
PWM
C1 to C3
6 to 8
CONFIGURATION
CYCLIC
SENSE
LIN
CONTROLLER
INH
2
INH
I/O BLOCK
9 to 16
P0 to P7
mdb488
Fig 1.
Block diagram
UJA1023
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 17 August 2010
3 of 49
NXP Semiconductors
UJA1023
LIN-I/O slave
6. Pinning information
6.1 Pinning
VIO
INH
BAT
LIN
GND
C1
C2
C3
1
2
3
4
16 P7
15 P6
14 P5
13 P4
UJA1023T
5
6
7
8
001aab877
12 P3
11 P2
10 P1
9
P0
Fig 2.
Pin configuration
6.2 Pin description
Table 3.
Symbol
VIO
INH
BAT
LIN
GND
C1
C2
C3
P0
P1
P2
P3
P4
P5
P6
P7
[1]
I = input;
O = output;
I/O = input or output.
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
[1]
I
O
I
I/O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
reference input for level adaptation of the I/O pins P0 to P7
inhibit output for controlling an external voltage regulator or internal
ADC
battery supply
LIN bus line
ground
configuration input 1 for LIN slave NAD assignment
configuration input 2 for LIN slave NAD assignment
configuration input / output 3 for LIN slave NAD assignment
bidirectional I/O pin 0
bidirectional I/O pin 1
bidirectional I/O pin 2
bidirectional I/O pin 3
bidirectional I/O pin 4
bidirectional I/O pin 5
bidirectional I/O pin 6
bidirectional I/O pin 7
UJA1023
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 17 August 2010
4 of 49
NXP Semiconductors
UJA1023
LIN-I/O slave
7. Functional description
The UJA1023 combines all blocks necessary to work as a stand-alone LIN slave. Various
I/O functions typically used in a car are supported. For a more detailed description refer to
Section 7.2
to
Section 7.6.
The block diagram is shown in
Figure 1.
7.1 Short description of the UJA1023
7.1.1 LIN controller
The LIN 2.0 controller monitors and evaluates the LIN messages in order to process the
LIN commands. It supervises and executes the NAD assignment, ID assignment and
I/O-configuration and controls the operating modes of the UJA1023.
The NAD configuration is done by a combination of a LIN master request frame and a
setting done by either a daisy chain or plug ID code.
7.1.2 LIN transceiver (including termination)
The LIN transceiver, which is LIN 2.0 / SAE J2602 compliant, is the interface between the
internal LIN controller and the physical LIN bus. The transmit data stream of the LIN
controller is converted into a bus signal with an optimized wave shape to minimize
electromagnetic emission. The required LIN slave termination of 30 kΩ is already
integrated. In case of LIN bus faults the UJA1023 switches to the low-power Limp home
mode.
7.1.3 Automatic bit rate detection
The automatic bit rate detection adapts to the LIN master’s bit rate. Any bit rate between
1 kbit/s and 20 kbit/s can be handled. This block checks whether the synchronization
break and synchronization field are valid. If not, the message will be rejected.
7.1.4 Oscillator
The on-chip oscillator provides the internal clock signal for some digital functions and is
the time reference for the automatic bit rate detection.
7.1.5 I/O block
The I/O block controls the configuration of the I/O pins. The LIN master configures the I/O
pin functionality by means of a master request frame and an optional slave response
frame.
Besides the standard level input and output behavior the following functions are also
handled by the UJA1023: local wake-up, cyclic input, edge capture, PWM output, switch
matrix I/O and AD conversion.
7.1.6 ADC
With three external components an 8-bit ADC function can be implemented. Each of the
eight bidirectional I/O pins can be used as input for the ADC, one at a time.
7.1.7 PWM
Each pin can be configured with a Pulse Width Modulation (PWM) function. The resolution
is 8-bit and the base frequency is approximately 2.7 kHz.
UJA1023
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 17 August 2010
5 of 49
