Preliminary
Features
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65536 x 16 bit static CMOS RAM
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15 and 20 ns Access Time
F
Common data inputs and
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F
F
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UL62H1616B
Low Voltage Automotive Fast 64K x 16 SRAM
Description
The UL62H1616B is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Lower / Upper Byte Read
- Word Read
- Lower / Upper Byte Write
- Word Write
- Standby
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L and W = H each address
change leads to a new Read cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G. If LB = L the data lower byte will
be available at the outputs DQ0-
DQ7, on UB = L the data upper
byte appear at the outputs DQ8-
DQ15. After the address change,
the data outputs go High-Z until the
new information is available. The
data outputs have no preferred
state. The Read cycle is finished by
the falling edge of W, or by the
rising edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
F
F
F
F
data outputs
Three-state outputs
Standby current < 50 µA at 125°C
Power supply voltage 2.5 V
Operating temperature range
K-Type:-40 °C to 85 °C
A-Type:-40 °C to 125 °C
CECC 90000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Package: SOP44 (525 mil)
Pin Configuration
A4
A3
A2
A1
A0
E
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
W
A15
A14
A13
A12
n.c.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
G
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
n.c.
A8
A9
A10
A11
n.c.
Pin Description
Signal Name
A0 - A15
DQ0 - DQ15
E
G
W
UB
LB
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Upper Byte Enable
Lower Byte Enable
Power Supply Voltage
Ground
not connected
SOP
Top View
November 01, 2001
1
UL62H1616B
Block Diagram
A7
A8
A9
A4
A11
A12
A13
A14
A15
A0
A1
A2
A3
A10
A5
A6
Row Address
Inputs
Row Decoder
Memory Cell
Array
512 Rows x
128 x 16 Columns
Preliminary
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
Common Data I/O
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
Address
Change
Detector
Clock
Generator
DQ13
DQ14
DQ15
Column Decoder
Column Address
Inputs
Sense Amplifier/
Write Control Logic
Truth Table
Operating Mode
Standby/not selected
Internal Read
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
* H or L
V
CC
V
SS
E W
G UB LB
E
H
L
L
L
L
L
L
L
L
W
*
H
*
H
H
H
L
L
L
G
*
H
*
L
L
L
*
*
*
LB
*
*
H
L
H
L
L
H
L
UB
*
*
H
H
L
L
H
L
L
DQ0-DQ7
High-Z
High-Z
Data Outputs Low-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
High-Z
Data Inputs High-Z
DQ8-DQ15
High-Z
High-Z
High-Z
Data Outputs Low-Z
Data Outputs Low-Z
High-Z
Data Inputs High-Z
Data Inputs High-Z
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 2.5 V. The timing reference level of all input and output signals is 1.2 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured ±200 mV from steady-state voltage.
Maximum Ratings
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Output Short-Circuit Current
at V
CC
= 2.5 V and V
O
= 0 V
**
K-Type
A-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
T
stg
| I
OS
|
Min.
-0.3
-0.3
-0.3
-
-40
-40
-65
Max.
3.6
V
CC
+ 0.3
V
CC
+ 0.3
1
85
125
150
100
Unit
V
V
V
W
°C
°C
mA
**
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
2
November 01, 2001
Preliminary
Recommended
Operating Conditions
Power Supply Voltage
Input Low Voltage
*
Symbol
V
CC
V
IL
V
IH
Conditions
Min.
2.3
-0.2
2.0
UL62H1616B
Max.
2.7
0.6
V
CC
+ 0.2
Unit
V
V
V
Input High Voltage
* -2 V at Pulse Width 10 ns
Electrical Characteristics
Supply Current - Operating Mode
Symbol
I
CC(OP)
V
CC
V
IL
V
IH
t
cW
t
cW
t
cW
V
CC
V
E
Conditions
=
=
=
=
=
=
2.7 V
0.6 V
2.0 V
35 ns
55 ns
60 ns
Min.
Max.
Unit
90
70
60
50
mA
mA
mA
µA
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(LVTTL level)
I
CC(SB)
= 2.7 V
= V
CC
- 0.2 V
= 2.7 V
= 2.0 V
I
CC(SB)1
V
CC
V
E
K-Type
A-Type
V
CC
I
OH
V
CC
I
OL
V
CC
V
IH
V
CC
V
IL
V
CC
V
OH
V
CC
V
OL
V
CC
V
OH
V
CC
V
OL
10
20
= 2.3 V
= -0.5 mA
= 2.3 V
= 0.5 mA
= 2.7 V
= 2.7 V
= 2.7 V
= 0V
=
=
=
=
2.3 V
2.0 V
2.3 V
0.4 V
2.0
0.4
2
-2
-0.5
0.5
mA
mA
V
V
µA
µA
mA
mA
Output High Voltage
Output Low Voltage
Input High Leakage Current
Input Low Leakage Current
Output High Current
Output Low Current
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
I
OHZ
I
OLZ
= 2.7 V
= 2.7 V
= 2.7 V
= 0V
2
-2
µA
µA
November 01, 2001
3
UL62H1616B
Switching Characteristics
Read Cycle
Read Cycle Time
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
LB, UB LOW to Data Valid
E HIGH to Output in High-Z
G HIGH to Output in High-Z
LB, UB HIGH to Output in High-Z
E LOW to Output in Low-Z
G LOW to Output in Low-Z
LB, UB LOW to Output in Low-Z
Output Hold Time from Address Change
E LOW to Power-Up Time
E HIGH to Power-Down Time
Symbol
Alt.
t
RC
t
AA
t
ACE
t
OE
t
B
t
HZCE
t
HZOE
t
HZB
t
LZCE
t
LZOE
t
LZB
t
OH
t
PU
t
PD
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
a(B)
t
dis(E)
t
dis(G)
t
dis(B)
t
en(E)
t
en(G)
t
en(B)
t
v(A)
4
0
0
3
0
15
Min.
Preliminary
15
Max.
Min.
20
Unit
Max.
15
15
15
7
7
7
7
7
20
20
20
9
9
8
8
8
4
0
0
3
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Write Cycle
Write Cycle Time
Write Pulse Width
Write Setup Time
Address Setup Time
Address Valid to End of Write
Chip Enable Setup Time
Byte Enable Setup Time
Pulse Width Chip Enable to End of Write
Pulse Width Byte Enable to End of Write
Data Setup Time
Data Hold Time
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
Symbol
Alt.
t
WC
t
WP
t
WP
t
AS
t
AW
t
CW
t
BW
t
CW
t
BW
t
DS
t
DH
t
AH
t
HZWE
t
HZOE
t
LZWE
t
LZOE
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
Min.
15
Max.
Min.
20
Unit
Max.
15
10
10
0
10
10
10
10
10
7
0
0
7
7
3
0
20
12
12
0
12
12
12
12
12
9
0
0
8
8
3
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
su(E)
t
su(B)
t
w(E)
t
w(B)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
dis(G)
t
en(W)
t
en(G)
4
November 01, 2001
Preliminary
Data Retention Mode
E - controlled
2.3 V
V
CC(DR)
≥
1.5 V
2.0 V
t
su(DR)
0V
Data Retention
t
rec
2.0 V
E
V
CC
UL62H1616B
V
CC(DR)
- 0.2 V
≤
V
E(DR)
≤
V
CC(DR)
+ 0.3 V
Data Retention
Characteristics
Data Retention Supply Voltage
Data Retention Supply Current
Data Retention Setup Time
Operating Recovery Time
Symbol
Conditions
Alt.
IEC
V
CC(DR)
I
CC(DR)
t
CDR
t
R
t
su(DR)
t
rec
V
CC(DR)
= 2 V
V
E
= V
CC(DR)
- 0.2 V
See Data Retention
Waveforms (above)
0
t
cR
1.5
2.7
30
V
µA
ns
ns
Min.
Typ.
Max.
Unit
Test Configuration for Functional Check
2.5 V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
E
W
G
LB
UB
V
CC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
V
SS
Simultaneous measure-
ment of all 16 output pins
V
IH
V
IL
Input level according to the
relevant test measurement
481
V
O
30 pF
1)
255
1)
In measurement of t
dis(E)
,t
dis(W)
, t
en(E)
, t
en(W)
, t
en(G)
the capacitance is 5 pF.
November 01, 2001
5
