DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG
SINGLE POWER SUPPLY DUAL OPERATIONAL AMPLIFIERS
<R>
DESCRIPTION
The
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG are dual operational amplifiers which are designed to
operate for a single power supply. It includes features of low-voltage operation, a common-mode input voltage that
range from V
−
(GND) level, an output from a V
−
(GND) level that is determined by the output stage of class C push-
pull circuit and a 50
μ
A(TYP.) constant current, and a low current consumption.
In addition, this can operate at both positive and negative power supply and it can be extensively used in various
amplifier circuits.
The
μ
PC1251GR-9LG,
μ
PC1251MP-KAA which expands temperature type is suited for wide operating ambient
temperature use, and
μ
PC358GR-9LG is used for general purposes.
A DC parameter selection that is compatible to operational amplifiers is also available.
μ
PC451GR-9LG,
μ
PC324GR-9LG which are quad types with the same circuit configuration are also available as
series of operational amplifiers.
<R>
FEATURES
• Input Offset Voltage
• Input Offset Current
• Large Signal Voltage Gain
• Small Package
The mounting area is reduced to 40% or 66% compared to the conventional 8-pin plastic SOP as shown in the
following diagram.
Package
Subject part number
Standard SOP
TSSOP
TSSOP (2.8 x 2.9)
±2
mV (TYP.)
±5
nA (TYP.)
100000 (TYP.)
• Internal frequency compensation
• Output short-circuit protection
μ
PC1251G2,
μ
PC358G2
μ
PC1251GR-9LG,
μ
PC358GR-9LG
μ
PC1251MP-KAA
Outline comparison
6.5
4.4
6.4
2.8
4.0
5.2
(Mounting area ratio)
(100%)
3.15
(60%)
2.9
(34%)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G17929EJ3V0DS00 (3rd edition)
Date Published December 2007 NS
Printed in Japan
2006, 2007
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG
<R>
ORDERING INFORMATION
Part Number
Selected Grade
Note
Package
8-pin plastic TSSOP (5.72 mm(225))
Package Type
•
12 mm wide embossed taping
•
Pin 1 on draw-out side
μ
PC1251GR-9LG-E1-A
μ
PC1251GR-9LG-E2-A
Standard
Note
Standard
8-pin plastic TSSOP (5.72 mm(225))
•
12 mm wide embossed taping
•
Pin 1 at take-up side
μ
PC1251GR(5)-9LG-E1-A
μ
PC1251GR(5)-9LG-E2-A
μ
PC1251MP-KAA-E1-A
μ
PC1251MP-KAA-E2-A
Note
DC
parameter selection
8-pin plastic TSSOP (5.72 mm(225))
•
12 mm wide embossed taping
•
Pin 1 on draw-out side
Note
DC
parameter selection
8-pin plastic TSSOP (5.72 mm(225))
•
12 mm wide embossed taping
•
Pin 1 at take-up side
Note
Standard
8-pin plastic TSSOP (2.8 x 2.9)
•
12 mm wide embossed taping
•
Pin 1 on draw-out side
Note
Standard
8-pin plastic TSSOP (2.8 x 2.9)
•
12 mm wide embossed taping
•
Pin 1 at take-up side
μ
PC1251MP(5)-KAA-E1-A
μ
PC1251MP(5)-KAA-E2-A
μ
PC358GR-9LG-E1-A
μ
PC358GR-9LG-E2-A
Note
Note
DC
parameter selection
8-pin plastic TSSOP (2.8 x 2.9)
•
12 mm wide embossed taping
•
Pin 1 on draw-out side
Note
DC
parameter selection
Standard
8-pin plastic TSSOP (2.8 x 2.9)
•
12 mm wide embossed taping
•
Pin 1 at take-up side
8-pin plastic TSSOP(5.72 mm(225))
•
12 mm wide embossed taping
•
Pin 1 on draw-out side
Note
Standard
8-pin plastic TSSOP(5.72 mm(225))
•
12 mm wide embossed taping
•
Pin 1 at take-up side
μ
PC358GR(5)-9LG-E1-A
μ
PC358GR(5)-9LG-E2-A
Note
DC
parameter selection
8-pin plastic TSSOP(5.72 mm(225))
•
12 mm wide embossed taping
•
Pin 1 on draw-out side
Note
DC
parameter selection
8-pin plastic TSSOP(5.72 mm(225))
•
12 mm wide embossed taping
•
Pin 1 at take-up side
Note
Pb-free (This product does not contain Pb in the external electrode and other parts.)
2
Data Sheet G17929EJ3V0DS
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG
EQUIVALENT CIRCUIT (1/2 Circuit)
V
+
<R>
PIN CONFIGURATION (Marking side)
100
μ
A
6
μ
A
Q
2
Q
1
Q
3
Q
4
6
μ
A
Q
5
C
C
Q
7
R
SC
OUT
Q
6
OUT1
I
I1
I
N1
V
−
1
2
3
4
1
− +
+ −
2
8
7
6
5
V
+
OUT2
I
I2
I
N2
I
I
+
I
N
−
Q
10
Q
8
Q
9
Q
11
Q
12
Q
13
50
μ
A
V
−
<R>
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Parameter
+
−
Note1
Symbol
+
−
μ
PC1251GR-9LG,
μ
PC1251GR(5)-9LG
μ
PC1251MP-KAA,
μ
PC1251MP(5)-KAA
−0.3
to
+32
±32
V
−
0.3 to V
+
32
V
−
0.3 to V
+
0.3
440
Indefinite
−
+
−
−
μ
PC358GR-9LG,
μ
PC358GR(5)-9LG
Unit
Voltage between V and V
Differential Input Voltage
Input Voltage
Note2
V
−
V
V
ID
V
I
V
V
V
V
mW
s
−40
to
+85
−55
to
+125
+
Output applied Voltage
Total Power Dissipation
Note3
Note4
Note5
V
O
P
T
t
S
T
A
T
stg
Output Short Circuit Duration
Operating Ambient Temperature
Storage Temperature
−40
to
+125
−55
to
+150
°C
°C
Note1.
Note that reverse connections of the power supply may damage ICs.
2.
The input voltage is allowed to input without damage or destruction independent of the magnitude of V . Either
input signal is not allowed to go negative by more than 0.3 V. In addition, the input voltage that operates
normally as an operational amplifier is within the Common Mode Input Voltage range of an electrical
characteristic.
3.
A range where input voltage can be applied to an output pin externally with no deterioration or damage to the
feature (characteristic). The input voltage can be applied regardless of the electric supply voltage. This
specification which includes the transition state such as electric power ON/OFF must be kept.
4.
This is the value of when the glass epoxy substrate (size: 100 mm x 100 mm, thickness: 1 mm, 15% of the
substrate area where only one side is copper foiled is filling wired) is mounted.
Note that restrictions will be made to the following conditions for each product, and the derating ratio
depending on the operating ambient temperature.
μ
PC1251GR-9LG: Derate at
−5.5
mW/°C when T
A
> 69°C.
(Junction
−
ambient thermal resistance R
th(J-A)
= 183°C/W)
μ
PC1251MP-KAA: Derate at
−4.8
mW/°C when T
A
> 58°C.
(Junction
−
ambient thermal resistance R
th(J-A)
= 208°C/W)
μ
PC358GR-9LG: Derate at
−5.5
mW/°C when T
A
> 44°C.
(Junction
−
ambient thermal resistance R
th(J-A)
= 183°C/W)
5.
Short circuits from the output to V can cause destruction. Pay careful attention to the total power dissipation
not to exceed the absolute maximum ratings,
Note 4.
+
Data Sheet G17929EJ3V0DS
3
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage (Split)
Power Supply Voltage (V = GND)
−
Symbol
V
V
±
+
MIN.
±1.5
+3
TYP.
MAX.
±15
+30
Unit
V
V
<R>
ELECTRICAL CHARACTERISTICS
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG (T
A
= 25°C, V
+
=
+5
V, V
−
= GND)
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Note1
Symbol
V
IO
I
IO
I
B
A
V
I
CC
CMR
SVR
V
O
V
ICM
I
O SOURCE
I
O SINK1
I
O SINK2
R
L
≥
2 kΩ
R
S
= 0
Ω
Conditions
MIN.
TYP.
±2
±5
14
MAX.
±7
±50
250
Unit
mV
nA
nA
Large Signal Voltage Gain
Circuit Current
Note2
25000
100000
0.7
1.2
mA
dB
dB
V
−
1.5
V
−
1.5
40
20
50
120
+
+
R
L
=
∞,
I
O
= 0 A
65
65
R
L
= 2 kΩ (Connect to GND)
0
0
V
IN (+)
=
+1
V, V
IN (−)
= 0 V
V
IN (−)
=
+1
V, V
IN (+)
= 0 V
V
IN (−)
=
+1
V, V
IN (+)
= 0 V, V
O
= 200 mV
f = 1 to 20 kHz
20
10
12
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage Swing
Common Mode lnput Voltage Range
Output Source Current
Output Sink Current
70
100
V
V
mA
mA
μ
A
dB
Channel Separation
μ
PC1251GR(5)-9LG,
μ
PC1251MP(5)-KAA,
μ
PC358GR(5)-9LG (T
A
= 25°C, V
+
=
+5
V, V
−
= GND)
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Note1
Symbol
V
IO
I
IO
I
B
A
V
I
CC
CMR
SVR
V
O
V
ICM
I
O SOURCE
I
O SINK1
I
O SINK2
R
L
≥
2 kΩ
R
S
= 0
Ω
Conditions
MIN.
TYP.
±2
±5
14
MAX.
±3
±50
60
Unit
mV
nA
nA
Large Signal Voltage Gain
Circuit Current
Note2
50000
100000
0.7
0.9
mA
dB
dB
V
−
1.5
V
−
1.4
40
20
50
120
70
+
+
R
L
=
∞,
I
O
= 0 A
65
65
R
L
= 2 kΩ (Connect to GND)
0
0
V
IN (+)
=
+1
V, V
IN (−)
= 0 V
V
IN (−)
=
+1
V, V
IN (+)
= 0 V
V
IN (−)
=
+1
V, V
IN (+)
= 0 V, V
O
= 200 mV
f = 1 to 20 kHz
30
15
30
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage Swing
Common Mode lnput Voltage Range
Output Source Current
Output Sink Current
70
100
V
V
mA
mA
μ
A
dB
Channel Separation
Notes1.
The input bias current flows in the direction where the IC flows out because the first stage is configured with a
PNP transistor.
2.
This is a current that flows in the internal circuit. This current will flow irrespective of the channel used.
4
Data Sheet G17929EJ3V0DS
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG
<R>
TYPICAL PERFORMANCE CHARACTERISTICS (T
A
= 25°C, TYP.) (Reference value)
P
T
vs. T
A
I
CC
vs. V
+
2
I
CC
- Supply Current - mA
R
L
=
∞
I
O
= 0 A
1.5
T
A
= 25°C
1
125°C
600
μ
P
P
T
- Total Power Dissipation - mW
LG
-9
R
G
51
12
A
PC
KA
μ
P-
1M
25
C1
500
400
300
200
With 100 mm x 100 mm,
100
0
0
thickness 1 mm glass epoxy
substrate (refer to "ABSOLUTE
MAXIMUM RATINGS Note 4"
)
μ
P
G
58
C3
9
R-
20
40
60
T
A
- Operating Ambient Temperature -
°C
V
IO
vs. V
+
LG
80
100
120
140
0.5
−40°C
0
0
10
20
30
40
V
+
- Power Supply Voltage - V (V
−
= GND)
V
IO
vs. T
A
3
V
IO
- Input Offset Voltage - mV
2
1
0
-1
-2
-3
V
+
=
+5
V, V
−
= GND
each 5 samples data
-50
0
50
100
150
3
V
IO
- Input Offset Voltage - mV
2
1
0
-1
-2
-3
0
10
20
30
40
V
+
- Power Supply Voltage - V (V
−
= GND)
T
A
- Operating Ambient Temperature -
°C
I
B
vs. V
+
30
30
I
B
vs. T
A
V
+
=
+15
V
I
B
- Input Bias Current - nA
20
I
B
- Input Bias Current - nA
V
−
= GND
20
10
10
0
0
10
20
30
40
V
+
- Power Supply Voltage - V (V
−
= GND)
0
-50
0
50
100
150
T
A
- Operating Ambient Temperature -
°C
Data Sheet G17929EJ3V0DS
5
