DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16315
1/4- to 1/12-DUTY FIP
TM
(VFD) CONTROLLER/DRIVER
DESCRIPTION
The
µ
PD16315 is a FIP (Fluorescent Indicator Panel, or Vacuum Fluorescent Display) controller/driver that is driven on a
1/4- to 1/12- duty factor. It consists of 16 segment output lines, 4 grid output lines, 8 segment/grid output drive lines, a
display memory, a control circuit, and a key scan circuit. Serial data is input to the
µ
PD16315 through a three-line serial
interface. This FIP controller/driver is ideal as a peripheral device for a single-chip microcomputer.
FEATURES
•
Multiple display modes: 16-segment & 12-digit to 24-segment & 4-digit
•
Key scanning: 16 x 2 matrix
•
Dimming circuit: 8 steps
•
High-withstanding-voltage output: V
DD
−
35 V MAX.
•
LED ports: 4 chs., 20 mA MAX.
•
No external resistors necessary for driver outputs: P-ch open-drain + pull-down resistor output
•
Serial interface: CLK, STB, D
IN
, D
OUT
ORDERING INFORMATION
Part Number
Package
44-pin Plastic QFP (10 x 10)
µ
PD16315GB-3BS
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S14074EJ1V0DS00 (1st edition)
Date Published February 2003 NS CP(K)
Printed in Japan
1999
µ
PD16315
1. BLOCK DIAGRAM
Command decoder
Dimming circuit
24-bit output latch
24
16
D
OUT
CLK
STB
Serial
interface
Display memory
24 bits x 12 words
Segment driver
D
IN
Seg
1
/KS
1
8
Seg
16
/KS
16
OSC
OSC
R
Timing generator
key scan
8
Multiplexed driver
Seg
17
/Grid
12
Data selector
Key data memory (2 x 16 bits)
12-bit shift register
Seg
24
/Grid
5
8
Key1, Key2
2
12
4
Grid driver
Grid
1
Grid
4
4-bit latch
V
DD
(+5 V)
LED
1
LED
4
V
SS
(0 V)
V
EE
(−30 V)
2
Data Sheet S14074EJ1V0DS
µ
PD16315
2. PIN CONFIGURATION (Top View)
44-pin Plastic QFP (10 x 10)
Seg
24
/Grid
5
Seg
23
/Grid
6
Seg
22
/Grid
7
Seg
21
/Grid
8
35
Seg
20
/Grid
9
34
Grid
1
Grid
2
Grid
3
40
44
V
SS
43
42
41
39
Grid
4
V
DD
38
37
36
LED
1
LED
2
LED
3
LED
4
OSC
D
OUT
D
IN
CLK
STB
KEY
1
KEY
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
Seg
19
/Grid
10
Seg
18
/Grid
11
Seg
17
/Grid
12
V
EE
Seg
16
/KS
16
Seg
15
/KS
15
Seg
14
/KS
14
Seg
13
/KS
13
Seg
12
/KS
12
Seg
11
/KS
11
Seg
10
/KS
10
V
DD
V
SS
Seg
1
/KS
1
Seg
2
/KS
2
Seg
3
/KS
3
Seg
4
/KS
4
Seg
5
/KS
5
Seg
6
/KS
6
Seg
7
/KS
7
Seg
8
/KS
8
Caution Use all of the power supply pins.
Seg
9
/KS
9
Data Sheet S14074EJ1V0DS
3
µ
PD16315
3. PIN FUNCTION
Symbol
D
IN
Pin Name
Data input
7
Pin No.
I/O
Input
Description
Input serial data at rising edge of shift clock, starting from the low
order bit.
D
OUT
Data output
6
Output
Output serial data at the falling edge of the shift clock, starting
from low order bit. This is N-ch open-drain output pin.
STB
Strobe
9
−
Initializes serial interface at the rising or falling edge of the
µ
PD16315. It then waits for reception of a command. Data input
after STB has fallen is processed as a command. While
command data is processed, current processing is stopped, and
the serial interface is initialized. While STB is high, CLK is
ignored.
CLK
Clock input
8
Input
Reads serial data at the rising edge, and outputs data at the
falling edge.
OSC
Oscillator pin
5
−
Connect resistor to this pin to determine the oscillation frequency
to this pin. Connect resistor between this pin and GND (V
SS
).
Seg
1
/KS
1
to
Seg
16
/KS
16
Grid
1
to Grid
4
High-withstanding-voltage 14 to 29
output (Segment)
High-withstanding-voltage 39 to 42
output (grid)
Seg
17
/Grid
12
to
Seg
24
/Grid
5
LED
1
to LED
4
KEY
1
, KEY
2
V
DD
V
SS
V
EE
High-withstanding-voltage 31 to 38
output (segment/grid)
LED output
Key data input
Logic power
Logic ground
Pull-down level
1 to 4
10, 11
13, 43
12, 44
30
Output
Input
−
−
−
CMOS output, +20 mA MAX.
Data input to these pins is latched at the end of the display cycle.
5 V
±
10%
Connect this pin to system GND.
V
DD
−
35 V MAX.
Output
These pins are selectable for segment or grid driving.
Output
Grid output pins
Output
Segment output pins (Dual function as key source)
4
Data Sheet S14074EJ1V0DS
µ
PD16315
4. DISPLAY RAM ADDRESS AND DISPLAY MODE
The display RAM stores the data transmitted to the
µ
PD16315 through the serial communication. The addresses are
allocated in 8-bit units.
Seg
1
Seg
4
00H
L
03H
L
06H
L
09H
L
Seg
8
00H
U
03H
U
06H
U
09H
U
0CH
U
0FH
U
12H
U
15H
U
18H
U
1BH
U
1EH
U
21H
U
Seg
12
01H
L
04H
L
07H
L
0AH
L
0DH
L
10H
L
13H
L
16H
L
19H
L
1CH
L
1FH
L
22H
L
Seg
16
01H
U
04H
U
07H
U
0AH
U
0DH
U
10H
U
13H
U
16H
U
19H
U
1CH
U
1FH
U
22H
U
Seg
20
02H
L
05H
L
08H
L
0BH
L
0EH
L
11H
L
14H
L
17H
L
1AH
L
1DH
L
20H
L
23H
L
Seg
24
02H
U
05H
U
08H
U
0BH
U
0EH
U
11H
U
14H
U
17H
U
1AH
U
1DH
U
20H
U
23H
U
DIG
1
DIG
2
DIG
3
DIG
4
DIG
5
DIG
6
DIG
7
DIG
8
DIG
9
DIG
10
DIG
11
DIG
12
0CH
L
0FH
L
12H
L
15H
L
18H
L
1BH
L
1EH
L
21H
L
b0
XXH
L
b3
b4
XXH
U
b7
Lower 4 bits
Higher 4 bits
Data Sheet S14074EJ1V0DS
5
