DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16638A
300/309-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
The
µ
PD16638A is a source driver for TFT-LCDs capable of supporting displays with 64-gray scales. Data input
is based on digital input configured as 6 bits by 3 dots (1 pixel), which can realize a full-color display of 260,000
colors by the output of 64 values that have been
γ
-corrected by an internal D/A converter and 2 sets of 9 external
power supplies. Because the output dynamic range is as large as 8.3 V
p-p
, level inversion operation of the LCD’s
common electrode is rendered unnecessary. Also, in order to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a non-chip 6-bit D/A
converter circuit whose odd output pins and even output pins output gray scale voltages of differing polarity.
Assuring a maximum clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to SVGA and XGA-
standard TFT-LCD panels.
FEATURES
•
CMOS level input
•
Output number selectable (300/309)
•
Input of 6 bits (gradation data) by 3 dots
•
Capable of outputting 64 values by means of 2 sets of 9 external power supplies (18 units) and a D/A converter
•
Output dynamic range 8.3 V
p-p
MIN. (@ V
DD2
= 8.5 V)
•
High-speed data transfer: f
MAX.
= 40 MHz (internal data transfer speed when operating at 3.0 V)
•
Applicable for dot-line inversion, n-line inversion and column line inversion
•
Single bank arrangement is possible (loaded with slim or bending TCP)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16638AN-×××
Remark
The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC
salesperson.
Document No. S13323EJ1V0DS00 (1st edition)
Date Published December 1998 NS CP(K)
Printed in Japan
The mark
shows major revised points.
©
1998
µ
PD16638A
BLOCK DIAGRAM
STHR
R,/L
CLK
O
sel
STB
STHL
V
DD1
(3.3V)
V
SS1
C
102
C
103
103-bit bidirectional shift register
C
1
C
2
D
00
to
D
05
D
10
to
D
15
D
20
to
D
25
Data register
POL2
POL
Latch
V
DD2
(8.5V)
Level shifter
V
SS2
V
0
to
V
17
D/A converter
Voltage follower output
S
1
S
2
S
3
S
300/309
RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
299/308
S
300/309
V
0
V
8
V
9
V
17
Multi-
plexer
9
6-bit D/A converter
9
POL
2
µ
PD16638A
PIN CONFIGURATION (
µ
PD16638AN-×××
×××)
×××
S
300/309
V
SS2
V
DD2
V
DD1
R,/L
D
20
D
21
D
22
D
23
D
24
D
25
POL
STB
STHL
CLK
O
sel
V
17
V
16
V
15
V
14
V
13
V
12
V
11
V
10
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
STHR
D
10
D
11
D
12
D
13
D
14
D
15
D
00
D
01
D
02
D
03
D
04
D
05
POL2
V
SS1
V
DD2
V
SS2
(Cupper Plated
surface)
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S
4
S
3
S
2
S
1
S
299/308
S
298/307
S
297/306
Remark
This figure does not specify the TCP package. LPC terminal is pulled up to the V
DD1
in the chip.
3
µ
PD16638A
1. PIN FUNCTIONS
Pin Symbol
S
1
to S
300/309
D
00
to D
05
D
10
to D
15
D
20
to D
25
R,/L
Shift direction control
input
These refer to the start pulse input/output pins when driver ICs are connected in
cascade. The shift directions of the shift registers are as follows.
R,/L = H : STHR input, S
1
→
S
300/309
, STHL output
R,/L = L : STHL input, S
300/309
→
S
1
, STHR output
R,/L = H : Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
R,/L = H : Becomes the start pulse output pin.
R,/L = L : Becomes the start pulse input pin.
This pin selects the number of output pins.
O
sel
= H: 300-output mode
O
sel
= L: 309-output mode
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge.
O
sel
= H: At the rising edge of the 100th clock after the start pulse input, the start
pulse output reaches the high level, thus becoming the start pulse of the next-
level driver.
O
sel
= L: At the rising edge of the 103rd clock after the start pulse input, the start
pulse output reaches the high level, thus becoming the start pulse of the next-
level driver.
The contents of the data register are transferred to the latch circuit at the rising
edge, and at the falling edge, the gray scale voltage is supplied to the driver. It is
necessary to ensure input of one pulse per horizontal period.
POL = H: The S
2n–1
output uses V
0
to V
8
as the reference supply. The S
2n
output
uses V
9
to V
17
as the reference supply.
POL = L : The S
2n–1
output uses V
0
to V
8
as the reference supply. The S
2n
output
uses V
0
to V
8
as the reference supply.
S
2n-1
indicates the odd output: and S
2n
indicates the even output. Input of the POL
signal is allowed the setup time(t
POL
-
STB
) with respect to STB’s rising edge.
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted.
Input the
γ
-corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
V
DD2
> V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
>
V
10
> V
11
> V
12
> V
13
> V
14
> V
15
> V
16
> V
17
> V
SS2
3.3 V
±0.3
V
Pin Name
Driver output
Display data input
Description
The D/A converted 64-gray-scale analog voltage is output.
The display data is input with a width of 18 bits, viz., the gray scale data (6 bits)
by 3 dots (1 pixels).
D
X0
: LSB, D
X5
: MSB
STHR
Right shift start pulse
input/output
Left shift start pulse
input/output
Number of output pins
select pin
STHL
O
sel
CLK
Shift clock input
STB
Latch input
POL
Polarity input
POL2
Data inversion
V
0
to V
17
γ
-corrected power
supplies
V
DD1
Test pin Logic power
supply
Driver power supply
Logic ground
Driver ground
V
DD2
V
SS1
V
SS2
8.0 V to 9.0 V
Grounding
Grounding
4
µ
PD16638A
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
to V
17
in that order.
Reverse this sequence to shut down. (Simultaneous power application to V
DD2
and V
0
to V
17
is
possible.)
2. To stabilize the supply voltage, be sure to insert a 0.1
µ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter, insertion of
a bypass capacitor of about 0.01
µ
F is also advised between the
γ
-corrected power supply
terminals (V
0
, V
1
, V
2
, ···, V
17
) and V
SS2
.
5
嵌入式系统
