DATA SHEET
µ
PD42S4260, 424260
4 M-BIT DYNAMIC RAM
256 K-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE
MOS INTEGRATED CIRCUIT
Description
The
µ
PD42S4260, 424260 are 262,144 words by 16 bits dynamic CMOS RAMs. The fast page mode and byte
read/write mode capability realize high speed access and low power consumption.
Besides, the
µ
PD42S4260 can execute CAS before RAS self refresh.
These are packaged in 44-pin plastic TSOP (II) and 40-pin plastic SOJ.
Features
• 262,144 words by 16 bits organization
• Single +5.0 V
±10
% power supply
• Fast access and cycle time
Part number
Power consumption
Active (MAX.)
880.0 mW
880.0 mW
797.5 mW
Access time
(MAX.)
60 ns
70 ns
80 ns
R/W cycle time
(MIN.)
110 ns
130 ns
150 ns
Fast page mode
cycle time (MIN.)
40 ns
45 ns
50 ns
µ
PD42S4260-60, 424260-60
µ
PD42S4260-70, 424260-70
µ
PD42S4260-80, 424260-80
• The
µ
PD42S4260 can execute CAS before RAS self refresh
Part number
Refresh cycle
512 cycles / 128 ms
Refresh
CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
Power consumption at standby
(MAX.)
0.825 mW
(CMOS level input)
µ
PD42S4260
µ
PD424260
512 cycles / 8 ms
5.5 mW
(CMOS level input)
• Multiplexed address inputs ... Row address: A0 to A8, Column address: A0 to A8
The information in this document is subject to change without notice.
Document No. M11089EJ5V0DSU1
1
©
1995
µ
PD42S4260, 424260
Ordering Information
Part number
Access time (MAX.)
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
40-pin Plastic SOJ
(400 mil)
44-pin Plastic TSOP (II)
(400 mil)
CAS before RAS refresh
RAS only refresh
Hidden refresh
40-pin Plastic SOJ
(400 mil)
Package
44-pin Plastic TSOP (II)
(400 mil)
Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
µ
PD42S4260G5-60
µ
PD42S4260G5-70
µ
PD42S4260G5-80
µ
PD42S4260LE-60
µ
PD42S4260LE-70
µ
PD42S4260LE-80
µ
PD424260G5-60
µ
PD424260G5-70
µ
PD424260G5-80
µ
PD424260LE-60
µ
PD424260LE-70
µ
PD424260LE-80
2
µ
PD42S4260, 424260
Pin Configurations
(Marking Side)
44-pin Plastic TSOP (II)
(400 mil)
40-pin Plastic SOJ
(400 mil)
V
CC
I/O1
I/O2
I/O3
I/O4
V
CC
I/O5
I/O6
I/O7
I/O8
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
GND
I/O16
I/O15
I/O14
I/O13
GND
I/O12
I/O11
I/O10
I/O9
V
CC
I/O1
I/O2
I/O3
I/O4
V
CC
I/O5
I/O6
I/O7
I/O8
NC
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
GND
I/O16
I/O15
I/O14
I/O13
GND
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
µ
PD42S4260G5
µ
PD424260G5
µ
PD42S4260LE
µ
PD424260LE
9
10
11
12
13
14
15
16
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
A0 to A8
RAS
UCAS
LCAS
WE
OE
V
CC
GND
NC
: Address Inputs
: Row Address Strobe
: Column Address Strobe (upper)
: Column Address Strobe (lower)
: Write Enable
: Output Enable
: Power Supply
: Ground
: No Connection
I/O1 to I/O16 : Data Inputs/Outputs
3
µ
PD42S4260, 424260
Block Diagram
RAS
LCAS
UCAS
WE
Clock Generator
Lower
Byte
Control
Data
Output
Buffer
OE
Upper
Byte
Control
V
CC
GND
CAS before
RAS Counter
Row Decoder
Data
Input
Buffer
Memory
Cell
Array
512
I/O1
to
I/O8
(Lower Byte)
A0
to
A8
Row
Address
Buffer
Column
Address
Buffer
X0 to X8
512
×
512
×
16
512
×
16
Data
Output
Buffer
×
16
I/O9
to
I/O16
(Upper Byte)
Data
Input
Buffer
Y0 to Y8
Sense Amplifier
512
Column Decoder
4
µ
PD42S4260, 424260
Input/Output Pin Functions
The
µ
PD42S4260, 424260 have input pins RAS, CAS
Note
, WE, OE, A0 to A8 and input/output pins I/O1 to
I/O16.
Pin name
RAS
(Row address
strobe)
Input/
Output
Input
Function
RAS activates the sense amplifier by latching a row address (A0 to A8) and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address (A0 to A8).
It also selects the following function.
• CAS before RAS refresh
Input
CAS activates data input/output circuit by latching column address (A0 to A8) and select-
ing a digit line connected with the sense amplifier.
CAS
(Column address
strobe)
A0 to A8
(Address input)
Input
9-bit address bus.
Input total 18-bit of address signal, upper 9-bit and lower 9-bit in sequence (address
multiplex method).
Therefore, one word (16-bit) is selected from 262,144-word by 16-bit memory cell array.
In actual operation, latch row address by specifying row address and activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (t
ASR
, t
ASC
) and hold time (t
RAH
, t
CAH
) are specified
for the activation of RAS and CAS.
Write control signal.
Write operation is executed by activating RAS, CAS and WE.
WE
(Write enable)
OE
(Output enable)
Input
Input
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
I/O1 to I/O16
(Data input/
output)
Input/
Output
16-bit data bus.
I/O1 to I/O16 are used to input/output data.
Note
CAS means UCAS and LCAS.
5
Microchip MCU
