DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4382161, 4382181, 4382321, 4382361
8M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Description
The
µ
PD4382161 is a 524,288-word by 16-bit, the
µ
PD4382181 is a 524,288-word by 18-bit, the
µ
PD4382321 is a
262,144-word by 32-bit and the
µ
PD4382361 is a 262,144-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using N-channel four-transistor memory cell.
The
µ
PD4382161,
µ
PD4382181,
µ
PD4382321 and
µ
PD4382361 integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The
µ
PD4382161,
µ
PD4382181,
µ
PD4382321 and
µ
PD4382361 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The
µ
PD4382161,
µ
PD4382181,
µ
PD4382321 and
µ
PD4382361 are packaged in 100-pin plastic LQFP with a 1.4 mm
package thickness for high density and low capacitive loading.
Features
•
Single 3.3 V power supply
•
Synchronous operation
•
Internally self-timed write control
•
Burst read / write : Interleaved burst and linear burst sequence
•
Fully registered inputs for flow through operation
•
All registers triggered off positive clock edge
•
LVTTL Compatible : All inputs and outputs
•
Fast clock access time : 8.5 ns (100 MHz), 9 ns (90 MHz) (
µ
PD4382321,
µ
PD4382361)
5
9 ns (90 MHz), 10 ns (83 MHz) (
µ
PD4382161,
µ
PD4382181)
•
Asynchronous output enable : /G
•
Burst sequence selectable : MODE
•
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
•
Separate byte write enable :
/BW1 - /BW4 (
µ
PD4382321,
µ
PD4382361), /BW1 - /BW2 (
µ
PD4382161,
µ
PD4382181), /BWE
Global write enable : /GW
•
Three chip enables for easy depth expansion
•
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14019EJ5V0DS00 (5th edition)
Date Published June 2000 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1999
µ
PD4382161, 4382181, 4382321, 4382361
Ordering Information
Part number
Access
Time
ns
Clock
Frequency
MHz
90
83
90
83
100
90
100
90
2
Core Supply
Voltage
V
3.3 ± 0.165
I/O
Interface
V
3.3 LVTTL
100-pin Plastic LQFP (14 x 20)
1
Package
Notes
µ
PD4382161GF-A90
9.0
10.0
9.0
10.0
8.5
9.0
8.5
9.0
5
µ
PD4382161GF-A10
µ
PD4382181GF-A90
5
µ
PD4382181GF-A10
µ
PD4382321GF-A85
µ
PD4382321GF-A90
µ
PD4382361GF-A85
µ
PD4382361GF-A90
Notes 1.
Grade A90 and A10 are available in the
µ
PD4382161GF and
µ
PD4382181GF
2.
Grade A85 and A90 are available in the
µ
PD4382321GF and
µ
PD4382361GF
2
Data Sheet M14019EJ5V0DS00
µ
PD4382161, 4382181, 4382321, 4382361
Pin Configurations (Marking Side)
/××× indicates active low signal.
100-pin Plastic LQFP (14 x 20)
[
µ
PD4382161GF,
µ
PD4382181GF]
/BWE
/BW2
/BW1
/ADV
/CE2
/GW
CLK
CE2
V
DD
V
SS
/CE
/AC
/AP
NC
NC
A6
A7
A8
A9
/G
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
NC
V
DD
NC
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
NC
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
V
SS
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
MODE
Remark
Refer to
Package Drawing
for 1-pin index mark.
A16
NC
NC
A5
A4
A3
A2
A1
A0
Data Sheet M14019EJ5V0DS00
3
µ
PD4382161, 4382181, 4382321, 4382361
Pin Identification (
µ
PD4382161GF,
µ
PD4382181GF)
Symbol
A0 - A18
Pin No.
37, 36, 35, 34, 33, 32, 100, 99, 82,
81, 44, 45, 46, 47, 48, 49, 50, 43, 80
I/O1 - I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9,
12, 13, 18, 19, 22, 23
I/OP1, NC
Note
I/OP2, NC
Note
/ADV
/AP
/AC
/CE, CE2, /CE2
/BW1, /BW2, /BWE
/GW
/G
CLK
MODE
74
24
83
84
85
98, 97, 92
93, 94, 87
88
86
89
31
Synchronous Data In,
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
V
DD
V
SS
V
DD
Q
V
SS
Q
NC
64
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,
38, 39, 42, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Asynchronous Power Down State Input
Power Supply
Ground
Output Buffer Power Supply
Output Buffer Ground
No Connection
Description
Synchronous Address Input
Note
NC (No Connection) is used in the
µ
PD4382161GF.
I/OP1 - I/OP2 is used in the
µ
PD4382181GF.
4
Data Sheet M14019EJ5V0DS00
µ
PD4382161, 4382181, 4382321, 4382361
100-pin Plastic LQFP (14 x 20)
[
µ
PD4382321GF,
µ
PD4382361GF]
/BWE
/BW4
/BW3
/BW2
/BW1
/ADV
/CE2
/GW
CE2
CLK
V
DD
V
SS
/AC
/CE
/AP
A6
A7
A8
A9
/G
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3, NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1, NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
Remark
Refer to
Package Drawing
for 1-pin index mark.
A16
V
SS
Data Sheet M14019EJ5V0DS00
5
